Freescale Semiconductor MPC8260 - Manual (Page 136)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-18 Freescale Semiconductor
2.4.1 PowerPC Cache Model
The PowerPC architecture does not define hardware aspects of cache implementations. For example, some
processors, including the PowerQUICC II’s processor core, have separate instruction and data caches
(Harvard architecture), while others implement a unified cache.
Microprocessors that implement the PowerPC architecture control the following memory access modes on
a page or block basis:
• Write-back/write-through mode
• Caching-inhibited mode
• Memory coherency
The PowerPC cache management instructions provide a means by which the application programmer can
affect the cache contents.
2.4.2 PowerQUICC II Implementation-Specific Cache Implementation
As shown in Figure 2-1 , the caches provide a 64-bit interface to the instruction fetch unit and load/store
unit. The surrounding logic selects, organizes, and forwards the requested information to the requesting
unit. Write operations to the cache can be performed on a byte basis, and a complete read-modify-write
operation to the cache can occur in each cycle.
Each cache block contains eight contiguous words from memory that are loaded from an 8-word boundary
(that is, bits A27–A31 of the effective addresses are zero); thus, a cache block never crosses a page
boundary. Misaligned accesses across a page boundary can incur a performance penalty.
The cache blocks are loaded in to the processor core in four beats of 64 bits each. The burst load is
performed as critical double word first.
To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the
processor core implements the MEI protocol. These three states, modified, exclusive, and invalid, indicate
the state of the cache block as follows:
• Modified—The cache block is modified with respect to system memory; that is, data for this
address is valid only in the cache and not in system memory.
• Exclusive—This cache block holds valid data that is identical to the data at this address in system
memory. No other cache has this data.
• Invalid—This cache block does not hold valid data.
2.4.2.1 Data Cache
As shown in Figure 2-6 , the data cache is configured as 128 sets of four blocks each. Each block consists
of 32 bytes, two state bits, and an address tag. The two state bits implement the three-state MEI
(modified/exclusive/invalid) protocol. Each block contains eight 32-bit words. Note that the PowerPC
architecture defines the term ‘block’ as the cacheable unit. For the PowerQUICC II’s processor core, the
block size is equivalent to a cache line.