Freescale Semiconductor MPC8260 - Manual (Page 875)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 28-27
• State 0—The first 3-5 bytes (depending on the contents of the LI field) are masked and then
compared with the first 3-5 bytes of the last SU. If there is a match, go to State 1, else remain in
State 0. The current SU will be received into a buffer descriptor.
• State 1—The first 3-5 bytes (depending on the contents of the LI field) are masked and then
compared with the first 3-5 bytes of the last SU. If there is a match, go to State 2, else go to State
0. The current SU will be received into a buffer descriptor.
• State 2—The first 3-5 bytes (depending on the contents of the LI field) are masked and then
compared with the first 3-5 bytes of the last SU. If there is a match, the current SU will be discarded
(unless there is an error), the channel will remain in state 2 and SU error monitor will be adjusted
accordingly. If the frames do not match, the current SU will be received into a buffer descriptor and
the channel will return to State 0.
28.3.4.4.3 Filtering Limitations
Because the algorithm is purely checking identical SUs, two FISUs will be received after each MSU rather
than merely one, even though they have the same sequence numbers.
Reception of an MSU resets the filtering algorithm. Also, reception of a short frame resets the filtering
algorithm when SS7_OPT[SF_DIS] = 0; however, when SS7_OPT[SF_DIS] = 1 (short frames are
discarded), the filtering algorithm remains unchanged.
28.3.4.4.4 Resetting the SU Filtering Mechanism
This command resets the filtering algorithm to ensure that the next SU will be received, even if it would
normally have been filtered. This command could be issued periodically so that the 603e core can check
to make sure that the link is really up and not simply receiving flags.
To issue this MCC command, refer to Section 14.4, “Command Set.” Use opcode 1110 (0xE).