Freescale Semiconductor MPC8260 - Manual (Page 566)

Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
14-18 Freescale Semiconductor
Figure 14-7. Dual-Port RAM Block Diagram
The dual-port RAM can be accessed by the following:
• CP load/store unit
• CP block transfer module (BTM)
• CP instruction fetcher (when executing microcode from RAM)
• G2 60x slave
• SDMA 60x bus
• SDMA local bus
Note that the dual-port RAM should not be cached.
Figure 14-8 shows the memory map of the dual-port RAM.
NOTE
Starting at address 0x4000 on .25
µm (HiP4) devices, an extra 8 Kbytes is
available for microcode execution only and cannot be used for data buffers
or BDs. However, when not used for microcode, the extra 8 Kbytes can be
accessed from the 60x bus for general purpose internal storage. On .29
µm
(HiP3) revisions of the PowerQUICC II, this space is reserved.
Slave Address
CP Instruction Address
CP Data Address
24 KBytes (HiP3)
Dual-Port RAM
(BDs, Buffers
and Microcode)
DMA (60x) Address
DMA (Local) Address
BTM Address
Slave Data
CP Instruction
CP Data
DMA (60x) Data
DMA (Local) Data
BTM Data
32 KBytes (HiP4)