Freescale Semiconductor MPC8260 - Manual (Page 1011)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-91
Table 30-48 describes FCCE fields.
30.13.4 FCC Transmit Internal Rate Registers (FTIRR x )
(FCC1 and FCC2 Only)
NOTE
The source clock of the internal rate timers is the BRGs clock, which is
configured in CMXUAR. THe frequency of this clock must be less than one
half of the FCC Tx clock of the UTOPIA interface.
0 4 5 6 7 8 9 10 11 12 13 14 15
Field — TIRU GRLI GBPB GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1 INTO0
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x11310 (FCCE1), 0x0x11330 (FCCE2), 0x0x11350 (FCCE3)/
0x0x11314 (FCCM1), 0x0x11334 (FCCM2), 0x0x11354 (FCCM3)
16 31
Field —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)
Figure 30-60. ATM Event Register (FCCE)/FCC Mask Register (FCCM)
Table 30-48. FCCE/FCCM Field Descriptions
Bits Name Description
0–4 — Reserved, should be cleared.
5 TIRU Transmit internal rate underrun. A cumulative lag of seven cells has formed between the
programmable rate and the actual rate for a specific Phy. A transmit internal rate counter expired
and a cell was not sent, either because of slow CPM performance or slow PHY performance. TIRU
may be set only when using transmit internal rate mode; see
Section 30.13.4, “FCC Transmit
Internal Rate Registers (FTIRRx) (FCC1 and FCC2 Only) .”
6 GRLI Global red-line interrupt. GRLI is set when a free buffer pool’s RLI flag is set. The RLI flag is also set
in the free buffer pool’s parameter table.
7 GBPB Global buffer pool busy interrupt. GBPB is set when a free buffer pool’s BUSY flag is set. The BUSY
flag is also set in the free buffer pool’s parameter table.
8–11 GINT x Global interrupt. Set when the number of events sent to the corresponding interrupt queue reaches
the corresponding event threshold. See
Section 30.11, “ATM Exceptions .”
12–15 INTO x Interrupt queue overflow. Set when an overflow condition occurs in the corresponding interrupt
queue. This occurs when the CP attempts to overwrite a valid interrupt entry. See
Section 30.11.1,
“Interrupt Queues .”
16–31 — Reserved, should be cleared.