Freescale Semiconductor MPC8260 - Manual (Page 657)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-13
19.6 IDMA Priorities
Each IDMA channel can be programmed to have a higher or lower priority relative to the serial controllers
or to have the lowest overall priority when requesting service from the CP. The IDMA priorities are
programmed in RCCR[DRxQP]; see
Section 14.3.7, “RISC Controller Configuration Register (RCCR).”
Take care to avoid overrun or underrun errors in the serial controllers when selecting high priorities for
IDMA.
Additional priority over all serial controllers can be selected by setting DCM[LP]; see Section 19.8.2.1,
“DMA Channel Mode (DCM).”
19.7 IDMA Interface Signals
Each IDMA has three dedicated handshake control signals for transfers involving an external peripheral
device: DMA request (DREQ[1–4]), DMA acknowledge (DACK[1–4]) and DMA done (DONE[1–4]).
DREQx may also be used to control the transfer pace of memory-to-memory transfers.
• DREQx is the external DMA request signal.
• DACKx is the DMA acknowledge.
• DONEx marks the end of an IDMA transfer.
The IDMA signals are multiplexed with other internal controller signals at the parallel I/O ports. To enable
the IDMA signals, the corresponding bits in the parallel I/O registers should be set. See
Chapter 40,
“Parallel I/O Ports.”
19.7.1 DREQ x and DACK x
When the peripheral requires IDMA service, it asserts DREQx and the PowerQUICC II begins the IDMA
process. When the IDMA service is in progress, DACKx is asserted during accesses to the peripheral. A
peripheral must validate the transfer by asserting TA or signal an error by asserting TEA.
If the user programs the memory controller for the peripheral, the PowerQUICC II asserts TA so that the
peripheral terminates DACKx. Without TA assertion, DACKx could be asserted for only one cycle, and
no data transfer occurs. To avoid peripherals mistaking this as a valid data transfer, DACKx should be
qualified with TA.
NOTE
Programming the parallel ports DREQ pins generates a transition on the
internal DREQ signals. This might cause an IDMA transaction, and, if the
IDMA is not initialized at that time, the IDMA transaction may lock the
CPM. Therefore, do one of the following:
• Program the parallel ports to be DREQ after initializing the IDMA
registers and parameter RAM.
• Pull down (pull-up does not help) the DREQ inputs before programming
the parallel port DREQ pins and until after setting the IDMA registers,
or program the IDMA registers for a dummy transaction before
programming the parallel port DREQ pins.