Freescale Semiconductor MPC8260 - Manual (Page 124)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-6 Freescale Semiconductor
The BPU contains an adder to compute branch target addresses and three user-control registers—the link
register (LR), the count register (CTR), and the CR. The BPU calculates the return pointer for subroutine
calls and saves it into the LR for certain types of branch instructions. The LR also contains the branch
target address for the Branch Conditional to Link Register (bclrx) instruction. The CTR contains the
branch target address for the Branch Conditional to Count Register (bcctrx) instruction. The contents of
the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather than
GPRs or FPRs, execution of branch instructions is largely independent from execution of other
instructions.
2.2.4 Independent Execution Units
The PowerPC architecture’s support for independent execution units allows implementation of processors
with out-of-order instruction execution. For example, because branch instructions do not depend on GPRs
or FPRs, branches can often be resolved early, eliminating stalls caused by taken branches.
In addition to the BPU, the processor core provides three other execution units and a completion unit,
which are described in the following sections.
2.2.4.1 Integer Unit (IU)
The IU executes all integer instructions. The IU executes one integer instruction at a time, performing
computations with its arithmetic logic unit (ALU), multiplier, divider, and XER register. Most integer
instructions are single-cycle instructions. Thirty-two general-purpose registers are provided to support
integer operations. Stalls due to contention for GPRs are minimized by the automatic allocation of rename
registers. The processor core writes the contents of the rename registers to the appropriate GPR when
integer instructions are retired by the completion unit.
2.2.4.2 Floating-Point Unit (FPU)
The FPU contains a single-precision multiply-add array and the floating-point status and control register
(FPSCR). The multiply-add array allows the processor core to efficiently implement multiply and
multiply-add operations. The FPU is pipelined so that single-precision instructions and double-precision
instructions can be issued back-to-back. Thirty-two floating-point registers are provided to support
floating-point operations. Stalls due to contention for FPRs are minimized by the automatic allocation of
rename registers. The core writes the contents of the rename registers to the appropriate FPR when
floating-point instructions are retired by the completion unit.
The processor core supports all IEEE 754 floating-point data types (normalized, denormalized, NaN, zero,
and infinity) in hardware, eliminating the latency incurred by software exception routines.
2.2.4.3 Load/Store Unit (LSU)
The LSU executes all load and store instructions and provides the data transfer interface between the
GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data
alignment, and provides sequencing for load/store string and multiple instructions.