6 cpm priority, 7 bus latency, 3 recovery from gun errors – Freescale Semiconductor MPC8260 User Manual

Page 890: Cpm priority -42, Bus latency -42, Recovery from gun errors -42, Gun error recovery—.29, Section 28.8.1.2.6

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Multi-Channel Controllers (MCCs)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

28-42

Freescale Semiconductor

28.8.1.2.6

CPM Priority

It is possible for the MCC to experience a GUN due to prioritization in the CPM. See

Section 14.3.5,

“Peripheral Interface,

for details on the CPM prioritization scheme. There are some options available for

altering how the CPM peripheral prioritization works. These options provide the opportunity for the user
to raise the priority of the MCC itself or lower the priority of other peripherals.

In .29

µm (HiP3) Rev C.2 and subsequent silicon, RCCR[MCCPR] controls the MCC priority in relation

to other CPM peripherals (refer to

Section 14.3.7, “RISC Controller Configuration Register (RCCR)”

).

When MCCPR is set, the MCCs are constantly at emergency priority level within the CPM prioritization
scheme. If used, this configuration should be tested to ensure that the setting of MCCPR does not have
adverse effects on the performance of other peripherals being used in an application. When MCCPR is
cleared, the normal priority scheme is be used (refer to

Section 14.3.5, “Peripheral Interface

).

Each FCC FIFO has threshold values, determined by the mode it is using, for determining normal and
emergency CPM request prioritization. When an FCC is in emergency mode, that FCC's TX or RX request
may have higher priority than MCC TX or RX. When FCC1 in particular is in emergency priority mode,
it will always be of higher priority than an MCC. This opens up the possibility of the FCC starving out the
MCC if the FCC continues to be overutilized. This can lead to a GUN. To help alleviate this situation,
setting FPSMR[TPRI] prevents the FCC’s TX from going into emergency mode and can minimize the risk
of global underrun.

28.8.1.2.7

Bus Latency

A GUN may also occur if the external memory bus bandwidth is insufficient for the system. Factors could
include a bus that is too slow or external masters keeping the bus for extended periods of time. Bus
parking master and bus arbiter configurations as described in

Section 4.3.2, “System Configuration and

Protection Registers,”

should also be considered as factors when making sure the CPM is properly

prioritized for bus access.

28.8.1.3

Recovery from GUN Errors

The GUN error is considered fatal because it cannot be determined which channel was at fault. In .29

µm

(HiP3) Rev. B.2 and earlier silicon, the only way to recover from MCC global underrun event is by
resetting the entire CPM. In .29

µm Rev. B.3 and subsequent silicon, the MCC Reset command was added

to CP command register [CPCR]. The MCC RESET provides a hard reset to the MCC FIFOs. Refer to the
following tables.

Table 28-20. GUN Error Recovery—.29

µm (HiP3) Rev A.1 and B.2 Silicon

Step

Action

1

Disable the TDM by clearing the appropriate enable bit in SIxGMR[4-7].

2

Reset the CPM by writing 0x8000_0000 to the CPCR (setting RST). This resets the registers and
parameters for all the channels as well as the CP and RISC timer tales.

3

Issue the INIT RX AND TX command to cover the channels in use.

4

Reprogram the specific MCC channel, global parameters, and any BDs that need to be updated.

5

Enable TDM by setting appropriate bit.

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