Freescale Semiconductor MPC8260 - Manual (Page 144)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-26 Freescale Semiconductor
TLB with memory. In the PowerQUICC II, the processor core’s TLBs are 64-entry, two-way
set-associative caches that contain instruction and data address translations. The PowerQUICC II’s
core provides hardware assist for software table search operations through the hashed page table
on TLB misses. Supervisor software can invalidate TLB entries selectively.
The MMU also directs the address translation and enforces the protection hierarchy programmed by the
operating system in relation to the supervisor/user privilege level of the access and in relation to whether
the access is a load or store.
2.6.2 PowerQUICC II Implementation-Specific MMU Features
The instruction and data MMUs in the processor core provide 4-Gbytes of logical address space accessible
to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte segment size.
The PowerQUICC II’s MMUs support up to 4 Petabytes (2 52 ) of virtual memory and 4 Gbytes (2 32 ) of
physical memory (referred to as real memory in the PowerPC architecture specification) for instructions
and data. Referenced and changed status is maintained by the processor for each page to assist
implementation of a demand-paged virtual memory system.
The PowerQUICC II’s TLBs are 64-entry, two-way set-associative caches that contain instruction and data
address translations. The processor core provides hardware assist for software table search operations
through the hashed page table on TLB misses. Supervisor software can invalidate TLB entries selectively.
After an effective address is generated, the higher-order bits of the effective address are translated by the
appropriate MMU into physical address bits. Simultaneously, the lower-order address bits (that are
untranslated and therefore, considered both logical and physical), are directed to the on-chip caches where
they form the index into the four-way set-associative tag array. After translating the address, the MMU
passes the higher-order bits of the physical address to the cache, and the cache lookup completes. For
caching-inhibited accesses or accesses that miss in the cache, the untranslated lower-order address bits are
concatenated with the translated higher-order address bits; the resulting 32-bit physical address is then
used by the system interface, which accesses external memory.
For instruction accesses, the MMU performs an address lookup in both the 64 entries of the ITLB, and in
the IBAT array. If an effective address hits in both the ITLB and the IBAT array, the IBAT array translation
takes priority. Data accesses cause a lookup in the DTLB and DBAT array for the physical address
translation. In most cases, the physical address translation resides in one of the TLBs and the physical
address bits are readily available to the on-chip cache.
When the physical address translation misses in the TLBs, the processor core provides hardware assistance
for software to search the translation tables in memory. When a required TLB entry is not found in the
appropriate TLB, the processor vectors to one of the three TLB miss exception handlers so that the
software can perform a table search operation and load the TLB. When this occurs, the processor
automatically saves information about the access and the executing context. Refer to the G2 Core reference
Manual for more detailed information about these features and the suggested software routines for
searching the page tables.