Freescale Semiconductor MPC8260 - Manual (Page 119)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 2-1
Chapter 2
G2 Core
The PowerQUICC II contains an embedded version of the MPC603e™ microprocessor. This chapter
provides an overview of the basic functionality of the processor core. For detailed information regarding
the processor refer to the following:
• G2 Core Reference Manual
• The Programming Environments for 32-Bit Implementation s of the PowerPC Architecture
This section describes the details of the processor core, provides a block diagram showing the major
functional units, and describes briefly how those units interact.
The signals associated with the processor core are described individually in Chapter 7, “60x Signals.”
Chapter 8, “The 60x Bus,” describes how those signals interact.
2.1 Overview
The processor core is a low-power implementation of the family reduced instruction set computing (RISC)
microprocessors that implement the PowerPC architecture. The processor core implements the 32-bit
portion of the PowerPC architecture, which supports 32-bit effective addresses.
Figure 2-1 is a block diagram of the processor core.