Freescale Semiconductor MPC8260 - Manual (Page 1238)

FCC HDLC Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
36-14 Freescale Semiconductor
36.9 HDLC Event Register (FCCE)/Mask Register (FCCM)
The FCCE is used as the HDLC event register when the FCC operates as an HDLC controller. The FCCE
reports events recognized by the HDLC channel and generates interrupts. On recognition of an event, the
HDLC controller sets the corresponding FCCE bit. FCCE bits are cleared by writing ones; writing zeros
does not affect bit values. All unmasked bits must be cleared before the CP clears the internal interrupt
request.
Interrupts generated by the FCCE can be masked in the HDLC mask register (FCCM), which has the same
bit format as FCCE. If an FCCM bit = 1, the corresponding interrupt in the event register is enabled. If the
bit is 0, the interrupt is masked.
Figure 36-7 represents the FCC/FCCM.
Table 36-9 describes FCCE/FCCM fields.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field
— GRA — TXE RXF BSY TXB RXB
Reset
0000_0000_0000_0000
R/W R/W
Addr 0x0x11310 (FCCE1), 0x0x11330 (FCCE2), 0x0x11350 (FCCE3)/
0x0x11314 (FCCM1), 0x0x11334 (FCCM2), 0x0x11354 (FCCM3)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field — FLG IDL —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)
Figure 36-7. HDLC Event Register (FCCE)/Mask Register (FCCM)