Freescale Semiconductor MPC8260 - Manual (Page 1219)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 35-23
Table 35-10 describes Ethernet RxBD fields.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E — W I L F CMR M BC MC LG NO SH CR OV CL
Offset + 2 Data Length
Offset + 4 Rx Data Buffer Pointer
Offset + 6
Figure 35-8. Fast Ethernet Receive Buffer (RxBD)
Table 35-10. RxBD Field Descriptions
Bits Name Description
0 E Empty
0 The buffer associated with this RxBD is full or reception terminated due to an error. The core can
examine or read to any fields of this RxBD. The CP does not use this BD as long as E = 0.
1 The associated buffer is empty. The RxBD and buffer are owned by the CP. Once E = 1, the core
should not write any fields of this RxBD.
1 — Reserved, should be cleared.
2 W Wrap (final BD in RxBD table)
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
RBASE points to in the table. The number of RxBDs in this table is programmable and determined
only by the W bit.
The RxBD table must contain more than one BD in Ethernet mode.
3 I Interrupt
0 No interrupt is generated after this buffer is used.
1 FCCE[RXB] or FCCE[RXF] are set when this buffer is used by the Ethernet controller. These two
bits can cause interrupts if they are enabled.
4 L Last in frame. Set by the Ethernet controller when this buffer is the last in a frame. This implies the
end of the frame or a reception error, in which case one or more of the CL, OV, CR, SH, NO, and LG
bits are set. The Ethernet controller writes the number of frame octets to the data length field.
0 Not the last buffer in a frame.
1 Last buffer in a frame.
5 F First in frame. Set by the Ethernet controller when this buffer is the first in a frame.
0 Not the first buffer in a frame.
1 First buffer in a frame.
6 CMR CAM match result for the frame. Set by the Ethernet controller when using a CAM for address
matching and FPSMR[ECM] = 1. Valid only if the L bit is set.
0 A hit in the CAM.
1 A miss in the CAM.
7 M Miss. Set by the Ethernet controller for frames that are accepted in promiscuous mode, but are
flagged as a miss by the internal address recognition. Thus, while using promiscuous mode, the
user uses the miss bit to determine quickly whether the frame is destined for this station. Valid only
if RxBD[I] is set.
0 The frame is received because the address is recognized.
1 The frame is received because of promiscuous mode (address is not recognized).