Freescale Semiconductor MPC8260 - Manual (Page 1082)

ATM AAL2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
32-20 Freescale Semiconductor
32.4 AAL2 Receiver
The following sections describe the AAL2 receiver.
32.4.1 Receiver Overview
The receiver cycle starts after the FCC receives a cell. If the cell header is successfully mapped to an ATM
channel number, the corresponding RCT is fetched and the AAL type is read. For AAL2 cells, the receiver
begins by checking if the last cell received in this channel (CID) has an uncompleted (split) packet. If so,
the receiver first finishes handling this packet.
The receiver then goes through a validation process. The receiver matches the OSF field in the STF with
the expected OSF based on the actual split packet (if the first packet is not split, the OSF should be zero).
If the two values do not match, an OSF error interrupt is issued and the receiver drops the last packet. Also,
if the STF parity check, the SN check or the OSF>47 check results in an error, the receiver issues an
interrupt and discards the whole cell. If any of the above errors has occurred and the cell has started with
the remainder of an uncompleted packet, the receiver does the following:
• For a CPS sublayer CID, the packet’s RxBD[UP] (uncompleted packet) bit is set.
• For an SSSAR sublayer CID, the buffer is closed with RxBD[RxError = US = 10] (uncompleted
SDU), and the rest of the frame is dropped.
The receiver now begins the process of extracting new CPS packets out of the cell with another round of
error checking. The receiver examines each CPS packet header for the following errors:
• Incorrect packet HEC. The packet and rest of the cell are discarded.
• Packet length (LI+1) is larger than CPS_Max_SDU_Length. The receiver discards the packet and
then continues to extract the next packet in the cell. However, if the packet belongs to an SSSAR
CID, the receiver closes the SSSAR buffer with RxBD[RxError = OS = 11] (oversized) and
discards the rest of the frame.
0x02 — Data
Length Contains the length of the buffer associated with this BD. If this is the last buffer (L=1)
and the UUI bit in the SSSAR TxQD is set, the 5-bit UUI field is located at
(TXDBPTR+Data Length)[3:7] with bit [3] being the msb, that is, in the byte (right
justified) immediately following the last byte of the buffer. For best bandwidth utilization
and optimized partitioning of the SDU to packets of exactly Seglen size when an SDU
is spread over multiple BD’s, the application should set Data Length to be an integer
multiple of Seg_Len. (Data Length == n x Seg_Len). For an SDU on a single BD this
restriction does NOT apply.
0x04 — TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. There are no
byte-alignment requirements for the buffer, and it may reside in either internal or
external memory. This value is not modified by the CP.
1 Boldfaced entries must be initialized by the user.
Table 32-5. SSSAR TxBD Field Descriptions (continued)
Offset Bits Name
1
Description