Freescale Semiconductor MPC8260 - Manual (Page 651)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-7
Figure 19-5 shows the IDMA transfer buffer.
Figure 19-5. IDMA Transfer Buffer in the Dual-Port RAM
Each buffer’s contents are transferred in three phases:
• First phase. The internal transfer buffer is filled with [EOB
(alignment to source address)
+ SS_MAX]
bytes, read from the source bus. Then, if EOB (alignment to destination address)
≤ EOB
(alignment to source
address) , [EOB (destination) + SS_MAX] bytes are written from the transfer buffer to the destination
bus; or if EOB (destination) > EOB (source) , [EOB (destination) + (k-2)*32] bytes are written bytes are
written. This write transfer size leaves a remainder of 0–31 bytes in the transfer buffer after the last
write burst of the steady-state phase. After the first phase, burst alignment is ensured.
• Steady-state phase. The transfer buffer is filled with SS_MAX bytes (k-1 bursts), read from the
source bus in STS units. Then, SS_MAX bytes are written to the destination bus, in DTS units,
from the transfer buffer. Because alignment is ensured from first phase, all bus transfers are bursts.
This sequence is repeated until there are no more than SS_MAX bytes to be transferred. A
remainder of 0–31 bytes is left in the transfer buffer after the last burst write.
• Last phase. The remaining data is read into the transfer buffer in bursts, with the last 1–31 bytes
read in single accesses. All data in the transfer buffer is written to the destination bus in bursts, with
the last 1–31 bytes written in single accesses. The last transfers, read/write or both can be
accompanied with DONE assertion, if programmed.
Figure 19-6 shows an example of the three IDMA transfer stages.
SS_MAX Initialized to (IDMA_transfer_buffer_size - 32) bytes, which is the steady-state maximum transfer size
of IDMA transfer. This condition ensures that the transfer buffer is either filled by one SS_MAX bytes
transfer and emptied in one or several transfers, or filled by one or several transfers to be emptied in
one SS_MAX bytes transfer. In terms of bursts, if the transfer buffer contains k bursts (each is 32 bytes
long), then SS_MAX equals to k-1 bursts which is (k-1)*32 bytes.
STS/DTS Source/destination transfer size. These parameters determine the access sizes in which the
source/destination is accessed in steady state of work. At least one of these values (DTS/STS) must
be initialized to the value of SS_MAX.
Table 19-3. IDMA Transfer Parameters (continued)
Parameter Description
SS_MAX
DMA_WRAP determines IDMA transfer buffer size
EOB[0–31]
32
64
96
0
128
(k-1)*32
(32 * k) bytes
Base Address (aligned to buffer size)