Freescale Semiconductor MPC8260 - Manual (Page 103)

Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 1-9
1.2.3 Communications Processor Module (CPM)
The CPM contains features that allow the PowerQUICC II to excel in a variety of applications targeted
mainly for networking and telecommunication markets.
The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP performance
and additional hardware and microcode routines that support high bit rate protocols like ATM (up to 155
Mbps full-duplex) and Fast Ethernet (100-Mbps full-duplex).
The following list summarizes the major features of the CPM:
• The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM local bus) from
the 60x bus (used by the system core). With this separate bus, the CP does not affect the
performance of the G2 core. The CP handles the lower layer tasks and DMA control activities,
leaving the G2 core free to handle higher layer activities. The CP has an instruction set optimized
for communications, but can also be used for general-purpose applications, relieving the system
core of small often repeated tasks.
• Two serial DMA (SDMA) that can do simultaneous transfers, optimized for burst transfers to the
60x bus and to the local bus.
• Three full-duplex, serial fast communications controllers (FCCs) supporting ATM (155 Mbps)
protocol through UTOPIA2 interface (there are two UTOPIA interfaces on the PowerQUICC II),
IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates (45 Mbps) and totally transparent
operation. Each FCC can be configured to transmit fully transparent and receive HDLC or
vice-versa. (Note that the MPC8250 does not support ATM (155 Mbps) protocol.)
• Two multichannel controllers (MCCs) (one on the MPC8250 and MPC8255) that can handle an
aggregate of 256 X 64 Kbps HDLC or transparent channels, multiplexed on up to eight TDM
interfaces. The MCC also supports super-channels of rates higher than 64 Kbps and subchanneling
of the 64-Kbps channels.
• Four full-duplex serial communications controllers (SCCs) supporting IEEE802.3/Ethernet, high-
level synchronous data link control, HDLC, local talk, UART, synchronous UART, BISYNC, and
transparent.
• Two full-duplex serial management controllers (SMC) supporting GCI, UART, and transparent
operations
• Serial peripheral interface (SPI) and I
2
C bus controllers
• Time-slot assigner (TSA) that supports multiplexing of data from any of the four SCCs, three
FCCs, and two SMCs.
1.3 Software Compatibility Issues
As much as possible, the PowerQUICC II CPM features were made similar to those of the previous
PowerQUICC devices (MPC860). The code flow ports easily from previous devices to the PowerQUICC
II, except for new protocols supported by the PowerQUICC II.
Although many registers are new, most registers retain the old status and event bits, so an understanding
of the programming models of the MC68360, MPC860, or MPC85015 is helpful. Note that the