Freescale Semiconductor MPC8260 - Manual (Page 648)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-4 Freescale Semiconductor
19.2.2 SDMA Mask Register (SDMR)
The SDMA mask register (SDMR) is an 8-bit read/write register with the same bit format as the SDMA
status register. If an SDMR bit is 1, the corresponding interrupt in SDSR is enabled. If the bit is zero, the
corresponding interrupt in the status register is masked. SDMR is cleared at reset. SDMR can be accessed
at 0x0x1101C.
19.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)
There are two 32-bit, read-only SDMA address registers. The PDTEA holds the system address accessed
during an SDMA transfer error on the 60x bus. The LDTEA holds the system address accessed during an
SDMA transfer error on the local/PCI bus. LDTEA is constantly updated with memory address of the local
bus access regardless of whether SDMA error on the local bus has occurred. The address value inside
LDTEA stops updating when SDSR[SBRE_L] is asserted. Both registers are undefined at reset. PDTEA
can be accessed at 0x0x10050; LDTEA can be accessed at 0x0x10058.
19.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)
There are two SDMA transfer error MSNUM registers (PDTEM and LDTEM). MSNUM[0–4] contains
the sub-block code (SBC) used to identify the current peripheral controller accessing the bus. MSNUM[5]
identifies which half of the controller is transferring (transmitter or receiver). The MSNUM of each
transaction is held in these registers until the transaction is complete.
PDTEM is for SDMA transfer errors on the 60x bus, and LDTEM is for errors on the local/PCI bus. Both
registers are undefined at reset. See
Figure 19-4 .
Table 19-2 describes PDTEM and LDTEM fields.
0 1 2 7
Field — MSNUM
1
Reset —
R/W R
Addr 0x0x10054 (PDTEM); 0x0x1005C (LDTEM)
1 On .29 µm (HiP3) , Rev A.1 devices, MSNUM = [0–5]. For .25µm (HiP4) and all other .29µm devices, MSNUM = [2–6].
Figure 19-4. SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM)
Table 19-2. PDTEM and LDTEM Field Descriptions
Bits
1
Name Description
0–1 —
2
Reserved, should be cleared.
2–6 MSNUM[2–6] 3 Bits 2–6 3 of MSNUM is the sub-block code of the current peripheral controller accessing the
bus. See the SBC field description of the CPCR in Section 14.4.1, “CP Command Register
(CPCR) .”
7 MSNUM[7] 4 Bit 7 4 of MSNUM indicates which section of the peripheral controller is accessing the bus.
0 Transmit section
1 Receive section