Table 9-51. iftpr field descriptions, Iftpr field descriptions -72, Bed in – Freescale Semiconductor MPC8260 User Manual

Page 378: Figure 9-66, Table 9-51

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PCI Bridge

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

9-72

Freescale Semiconductor

Figure 9-66. Inbound Free_FIFO Tail Pointer Register (IFTPR)

9.12.3.2.2

Inbound Post_FIFO Head Pointer Register (IPHPR) and
Inbound Post_FIFO Tail Pointer Register (IPTPR)

The inbound post FIFO holds MFAs from external PCI masters which are posted to the local processor.
PCI masters, external to the PCI bridge, write to the head of the FIFO by writing the MFA to IFQPR (refer
to

Section 9.12.3.4.1, “Inbound FIFO Queue Port Register (IFQPR)”

). The I

2

O unit transfers the MFA to

the location pointed to by the IPHPR. The local address is QBAR + IPHPR.

Once the MFA has been written to the queue in local memory, the PCI bridge’s I

2

O unit advances the

IPHPR to set up for the next message. This causes an interrupt to be asserted to the local processor. The
inbound post queue interrupt bit in the inbound interrupt status register (IMISR[IPQI]) is set to indicate
this condition (refer to

Table 9-62

). The local processor acknowledges the message (i.e. MFA) by writing

a one to the appropriate status bit (IMISR[IPQI]) to clear it. The local processor fetches the MFA by
reading the contents of the IPTPR. After the local processor has read the message pointed to by the MFA,
the local processor must advance the IPTPR. Once the processor has completed use of the message, it must
return the message buffer (i.e. MFA) to the inbound free list FIFO.

PCI masters post MFAs to the inbound post list FIFO that is pointed to by the inbound post_FIFO head
pointer register, described in

Figure 9-67

and

Table 9-52

. The PCI writes are addressed to the inbound

queue port. Hardware (in the I

2

O module) automatically advances the IPHPR after every write.

31

20

19

16

Field

QBA

IFTP

Reset

0000_0000_0000_0000

R/W

R

R/W

Addr

0x104AA

15

2

1

0

Field

IFTP

Reset

0000_0000_0000_0000

R/W

R/W

R

Addr

0x104A8

Table 9-51. IFTPR Field Descriptions

Bits

Name

Description

31–20

QBA

Queue base address. When read returns the contents of QBAR bits 31-20.

19–2

IFTP

Inbound free_FIFO tail pointer. Local memory offset of the tail pointer of the inbound free list FIFO.

1–0

Reserved, should be cleared.

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