Freescale Semiconductor MPC8260 - Manual (Page 303)

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 8-29
Figure 8-10. Burst Transfer to 32-Bit Port Size
8.5.6 Data Bus Termination by Assertion of TEA
If a device initiates a transaction that is not supported by the PowerQUICC II, the PowerQUICC II signals
an error by asserting TEA. Because the assertion of TEA is sampled by the device only during the data
tenure of the bus transaction, the PowerQUICC II ensures that the device master receives a qualified data
bus grant by asserting DBG before asserting TEA. The data tenure is terminated by a single assertion of
TEA regardless of the port size or whether the data tenure is a single-beat or burst transaction. This
sequence is shown in Figure 8-11.. In Figure 8-11. the data bus is busy at the beginning of the transaction,
thus delaying the assertion of DBG. Note that data errors (parity and ECC) are reported not by assertion of
TEA but by assertion of MCP.
Because the assertion of TEA is sampled by the device only during the data tenure of the bus transaction,
the PowerQUICC II ensures that the device receives a qualified data bus grant by asserting DBG before
asserting TEA. The data tenure is terminated by a single assertion of TEA regardless of the port size or
whether the data tenure is a single-beat or burst transaction. This sequence is shown in
Figure 8-11 . In
Figure 8-11 the data bus is busy at the beginning of the transaction, thus delaying the assertion of DBG.
CLKOUT
ADDR + ATTR
TS
AACK
DBG
PSDVAL
D[0–31]
TA
D0 D1 D2 D3 D4 D5 D6 D7