Freescale Semiconductor MPC8260 - Manual (Page 912)

Fast Communications Controllers (FCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
29-14 Freescale Semiconductor
29.8 Interrupts from the FCCs
Interrupt handling for each of the FCC channels is configured on a global (per channel) basis in the
interrupt pending register (SIPNR_L) and interrupt mask register (SIMR_L). One bit in each register is
used to either mask, enable, or report an interrupt in an FCC channel. The interrupt priority between the
FCCs is programmable in the CPM interrupt priority register (SCPRR_H). The interrupt vector register
(SIVEC) indicates which pending channel has highest priority. Registers within the FCCs manage
interrupt handling for FCC-specific events.
Events that can cause the FCC to interrupt the processor vary slightly among protocols and are described
with each protocol. These events are handled independently for each channel by the FCC event and mask
registers (FCCE and FCCM).
29.8.1 FCC Event Registers (FCCE x )
Each FCC has an FCC event register (FCCE) used to report events. On recognition of an event, the FCC
sets its corresponding FCCE bit regardless of the corresponding mask bit. To the user it appears as a
memory-mapped register that can be read at any time. Bits are cleared by writing ones; writing zeros has
Table 29-5. FCR x Field Descriptions
Bits Name Description
0 — Reserved, should be cleared.
1 FCCP FCC priority. Used in conjunction with PPC_ACR[PRKM] (see section 4.3.2.2) and
LCL_ACR[PRKM] (see section 4.3.2.4) for a low request level.
0 Disables CPM low request level to refer to FCCs and MCCs.
1 Enables CPM low request level to refer to FCCs and MCCs.
2 GBL Global. Indicates whether the memory operation should be snooped.
0 Snooping disabled.
1 Snooping enabled.
3–4 BO Byte ordering. Used to select the byte ordering of the buffer. If BO is modified on-the-fly, it takes
effect at the start of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next
BD.
01 Munged little-endian byte ordering. As data is sent onto the serial line from the data buffer, the
LSB of the buffer double-word contains data to be sent earlier than the MSB of the same buffer
double-word.
10 Freescale byte ordering (normal operation). It is also called big-endian byte ordering. As data is
sent onto the serial line from the data buffer, the MSB of the buffer word contains data to be sent
earlier than the LSB of the same buffer word.
5 TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6 DTB Indicates on what bus the data is located.
0 On the 60x bus.
1 On the local.
7 BDB Indicates on what bus the BDs are located.
0 On the 60x bus.
1 On the local bus.