Freescale Semiconductor MPC8260 - Manual (Page 454)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-36 Freescale Semiconductor
11.4.4 Page-Mode Support and Pipeline Accesses
The SDRAM interface supports back-to-back page mode. A page remains open as long as back-to-back
accesses that hit the page are generated on the bus. The page is closed once the bus becomes idle unless
ORx[PMSEL] is set.
The use of SDRAM pipelining allows data phases to occur on with zero bubbles for CPM accesses and
with one bubble for core accesses, as required by the 60x bus specification.
If ETM/LETM = 1, the use of SDRAM pipelining also allows for back-to-back data phases to occur with
zero clocks of separation for CPM accesses and with one clock of separation for core accesses, as required
by the 60x bus specification.
Table 11-19. SDRAM Interface Commands
Command Description
BANK - ACTIVATE Latches the row address and initiates a memory read of that row. Row data is latched in SDRAM
sense amplifiers and must be restored with a
PRECHARGE command before another BANK - ACTIVATE
is issued.
MODE - SET Allows setting of SDRAM options—CAS latency, burst type, and burst length. CAS latency depends
on the SDRAM device used (some SDRAMs provide CAS latency of 1, 2, or 3; some provide a
latency of 1, 2, 3, or 4, etc.). Burst type must be chosen according to the 60x cache wrap
(sequential). Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, PowerQUICC II
supports only a 4-beat burst for 64-bit port size and an 8-beat burst for 32-bit port size.
PowerQUICC II does not support burst lengths of 1, 2, and a page for SDRAMs. The mode register
data (CAS latency, burst length, and burst type) is programmed into the P/LSDMR register by
initialization software at reset. After the P/LSDMR is set, the PowerQUICC II transfers the
information to the SDRAM array by issuing a
MODE - SET command. Section 11.4.9, “SDRAM
Mode-Set Command Timing ,” gives timing information.
PRECHARGE
( SINGLE
BANK / ALL BANKS )
Restores data from the sense amplifiers to the appropriate row. Also initializes the sense amplifiers
to prepare for reading another row in the SDRAM array. A
PRECHARGE command must be issued
after a read or write if the row address changes on the next access. Note that the PowerQUICC II
uses the SDA10 pin to distinguish the
PRECHARGE - ALL - BANKS command. The SDRAMs must be
compatible with this format.
READ Latches the column address and transfers data from the selected sense amplifier to the output buffer
as determined by the column address. During each successive clock, additional data is output
without additional
READ commands. The amount of data transferred is determined by the burst size.
At the end of the burst, the page remains open.
REFRESH Causes a row to be read in both memory banks (JEDEC SDRAM) as determined by the refresh row
address counter (similar to CBR). The refresh row address counter is internal to the SDRAM device.
After being read, a row is automatically rewritten into the memory array. Both banks must be in a
precharged state before executing
REFRESH .
WRITE Latches the column address and transfers data from the data signals to the selected sense amplifier
as determined by the column address. During each successive clock, additional data is transferred
to the sense amplifiers from the data signals without additional
WRITE commands. The amount of
data transferred is determined by the burst size. At the end of the burst, the page remains open.