Table 19-9. idsr/idmr field descriptions, 5 idma bds, Idma bds -24 – Freescale Semiconductor MPC8260 User Manual

Page 668: Idma event/mask registers (idsr/idmr) -24, Idsr/idmr field descriptions -24, Section 19.8.4, “idma event register (idsr), And mask register (idmr), Section 19.8.4, Section 19.8.4, “idma, Event register (idsr) and mask register (idmr)

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SDMA Channels and IDMA Emulation

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

19-24

Freescale Semiconductor

transfer sizes allows longer transfers to memory devices, optimizes bus usage and thus reduces the overall
load on the CP.

For example, 2,016 bytes can be transferred by issuing one

START

_

IDMA

command using a 2-Kbyte

internal transfer buffer, or by issuing 63

START

_

IDMA

commands using a 64-byte buffer. The load on the

CP in the second case is about 63 times more than the first.

19.8.4

IDMA Event Register (IDSR) and Mask Register (IDMR)

The IDMA event (status) register (IDSR) is used to report events recognized by the IDMA controller. On
recognition of an event, the controller sets the corresponding IDSR bit. Each IDMA event bit can generate
a maskable interrupt to the core. Even bits are cleared by writing ones; writing zeros has no effect.

The IDMA mask register (IDMR) has the same format as IDSR. Setting IDMR bits enables, and clearing
IDMR bits disables, the corresponding interrupts in the event register.

Figure 19-10

shows the bit format for IDSR and IDMR.

Table 19-9

describes IDSR/IDMR fields.

19.8.5

IDMA BDs

Source addresses, destination addresses, and byte counts are presented to the CP using the special IDMA
BDs. The CP reads the BDs, programs the SDMA channel, and notifies the core about the completion of
a buffer transfer using the IDMA BDs. This concept is similar to the one used for the serial controllers on
the PowerQUICC II except that the BD is larger because it contains additional information.

0

3

4

5

6

7

Field

SC

OB

EDN

BC

Reset

0000_0000

R/W

R

R/W

Addr

0x0x11020 (IDSR1), 0x0x11028 (IDSR2), 0x0x11030 (IDSR3), 0x0x11038 (IDSR4)/

0x0x11024 (IDMR1), 0x0x1102C (IDMR2), 0x0x11034 (IDMR3), 0x0x1103C (IDMR4)

Figure 19-10. IDMA Event/Mask Registers (IDSR/IDMR)

Table 19-9. IDSR/IDMR Field Descriptions

Bits

Name

Description

0–3

Reserved, should be cleared.

4

SC

Stop completed. Set after the IDMA channel completes processing the

STOP

_

IDMA

command. Do

not change channel parameters until SC is set.

5

OB

Out of buffers. Set to indicate that the IDMA channel encountered no valid BDs for the transfer.

6

EDN

External DONE was asserted by device. Set to indicate that the IDMA channel terminated a transfer
because DONE was asserted by an external device, on the former SDMA transaction.

7

BC

BD completed. Set only after all data of a BD whose I (interrupt) bit is set has completed transfer to
the destination.

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