Freescale Semiconductor MPC8260 - Manual (Page 585)

Serial Interface with Time-Slot Assigner
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 15-9
15.4.1 One Multiplexed Channel with Static Frames
The example in Figure 15-5. shows one of many possible settings. With this configuration, the SIx RAM
has 256 entries for transmit data and strobe routing and 256 entries for receive data and strobe routing. This
configuration should be chosen only when one TDM is required and the routing on that TDM does not
need to be dynamically changed. The number of entries available in the SIx RAM is determined by the
user.
Figure 15-5. One TDM Channel with Static Frames and Independent Rx and Tx Routes
15.4.2 One Multiplexed Channel with Dynamic Frames
In the configuration shown in Figure 15-6., one multiplexed channel has 256 entries for transmit data and
strobe routing and 256 entries for receive data and strobe routing. Each RAM has two sections, the
current-route RAM and a shadow RAM for changing serial routing dynamically.
After programming the shadow RAM, the user sets SIxCMDR[CSRxn] for the associated channel. When
the next frame sync arrives, the SI automatically exchanges the current-route RAM for the shadow RAM.
See
Section 15.4.5, “Static and Dynamic Routing.”
256 Entries
TXa
Route
Framing Signals
L1TCLKa x
L1TSYNCa x
SI x RAM address:
256 Entries
RXa
Route
511
1535
1024
L1RCLKa x
L1RSYNCa x
(each entry is16 bits wide)
0