Freescale Semiconductor MPC8260 - Manual (Page 1261)

Serial Peripheral Interface (SPI)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 38-15
38.7.1.2 SPI Transmit BD (TxBD)
Data to be sent with the SPI is sent to the CP by arranging it in buffers referenced by TxBDs in the TxBD
table. TxBD fields should be prepared before data is sent. The format of an TxBD is shown in
Figure 38-12 .
Table 38-9 describes the TxBD status and control fields.
4 L Last. Updated by the SPI when the buffer is closed because SPISEL was negated (slave mode
only). Otherwise, RxBD[ME] is set. The SPI updates L after received data is placed in the buffer.
0 This buffer does not contain the last character of the message.
1 This buffer contains the last character of the message.
5 — Reserved, should be cleared.
6 CM Continuous mode. Master mode only; in slave mode, CM should be cleared.
0 Normal operation.
1 The CP does not clear RxBD[E] after this BD is closed; the buffer is overwritten when the CP next
accesses this BD. This allows continuous reception from an SPI slave into one buffer for
autoscanning of a serial A/D peripheral with no core overhead.
7–13 — Reserved, should be cleared.
14 OV Overrun. Set when a receiver overrun occurs during reception (slave mode only). The SPI updates
OV after the received data is placed in the buffer.
15 ME Multimaster error. Set when this buffer is closed because SPISEL was asserted when the SPI was
in master mode. Indicates a synchronization problem between multiple masters on the SPI bus. The
SPI updates ME after the received data is placed in the buffer.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 R — W I L — CM — UN ME
Offset + 2 Data Length
Offset + 4 Tx Buffer Pointer
Offset + 6
Figure 38-12. SPI TxBD
Table 38-9. SPI TxBD Status and Control Field Descriptions
Bits Name Description
0 R Ready.
0 The buffer is not ready to be sent. This BD or its buffer can be modified. The CP clears R (unless
RxBD[CM] is set) after the buffer is sent (unless RxBD[CM] is set) or an error occurs.
1 The buffer is ready for transmission or is being sent. The BD cannot be modified once R is set.
1 — Reserved, should be cleared.
Table 38-8. SPI RxBD Status and Control Field Descriptions (continued)
Bits Name Description