Freescale Semiconductor MPC8260 - Manual (Page 773)

SCC Transparent Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 24-3
24.4 Achieving Synchronization in Transparent Mode
Once the SCC transmitter is enabled for transparent operation, the TxBD is prepared and the transmit FIFO
is preloaded by the SDMA channel, another process must occur before data can be sent. It is called transmit
synchronization. Similarly, once the SCC receiver is enabled for transparent operation in the GSMR and
the RxBD is made empty for the SCC, receive synchronization must occur before data can be received. An
in-line synchronization pattern or an external synchronization signal can provide bit-level control of the
synchronization process when sending or receiving.
24.4.1 Synchronization in NMSI Mode
This section describes synchronization in NMSI mode.
24.4.1.1 In-Line Synchronization Pattern
The transparent channel can be programmed to receive a synchronization pattern. This pattern is defined
in the data synchronization register, DSR; see
Section 20.1.3, “Data Synchronization Register (DSR).”
Pattern length is specified in GSMR_H[SYNL], as shown in Table 24-1 . See also Section 20.1.1, “The
General SCC Mode Registers (GSMR1–GSMR4).”
If a 4-bit SYNC is selected, reception begins as soon as these four bits are received, beginning with the
first bit following the 4-bit SYNC. The transmitter synchronizes on the receiver pattern if
GSMR_H[RSYN] = 1.
NOTE
The transparent controller does not automatically send the synchronization
pattern; therefore, the synchronization pattern must be included in the
transmit buffer.
24.4.1.2 External Synchronization Signals
If GSMR_H[SYNL] is 0b00, the transmitter uses CTS and the receiver uses CD to begin the sequence.
These signals share two options—pulsing and sampling.
GSMR_H[CDP] and GSMR_H[CTSP] determine whether CD or CTS need to be asserted only once to
begin reception/transmission or whether they must remain asserted for the duration of the transparent
Table 24-1. Receiver SYNC Pattern Lengths of the DSR
GSMR_H[SYNL]
Setting
Bit Assignments
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
00 An external SYNC signal is used instead of the SYNC pattern in the DSR.
01 4-bit
10 8-bit
11 16-bit