Freescale Semiconductor MPC8260 - Manual (Page 554)

Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
14-6 Freescale Semiconductor
Figure 14-2. Communications Processor (CP) Block Diagram
14.3.4 G2 Core Interface
The CP communicates with the G2 core in several ways:
General-
Load/Store
Unit
Block Transfer
Dual-Port RAM
Microcode
DMA
Execution
Source Buses
Destination Bus
Address
Data
Address
Data
Ad
dr
es
s
Da
ta
Pe
ri
pher
al
Bu
s
Scheduler
Decoder
Instruction
To all units
Bus
Communications Processor (CP)
Timer
Special
Sequencer
Registers Unit
Data
Ad
dr
es
s
Da
ta
Data
ROM In
st
ru
ct
io
n
Addr
ess
Add
res
s
Dat
a
Interface
Local Bus
60x Bus
Module
(BTM)
Purpose
Registers