Freescale Semiconductor MPC8260 - Manual (Page 133)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 2-15
2.3.1.2.4 Processor Version Register (PVR)
Software can identify the PowerQUICC II’s processor core by reading the processor version register
(PVR). The processor version number for .29
µm (HiP3) devices is 0x00810101 and 0x80811014 for
.25
µm (HiP4) devices.
2.3.2 PowerPC Instruction Set and Addressing Modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent
among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This
fixed instruction length and consistent format greatly simplifies instruction pipelining.
2.3.2.1 Calculating Effective Addresses
The effective address (EA) is the 32-bit address computed by the processor when executing a memory
access or branch instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
• EA = (rA|0) + offset (including offset = 0) (register indirect with immediate index)
• EA = (rA|0) + rB (register indirect with index)
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the
effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address, the memory operand is considered to wrap around from the maximum
effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned binary
arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
In addition to the functionality of the MPC603e, the PowerQUICC II has additional hardware support for
misaligned little-endian accesses. Except for string/multiple load and store instructions, little-endian
load/store accesses not on a word boundary generate exceptions under the same circumstances as
big-endian requests.
24–26 DWLCK Data cache way lock. Useful for locking blocks of data into the data cache for time-critical
applications where deterministic behavior is required. See Section 2.4.2.3, “Cache Locking.”
27–31 — Reserved
Table 2-3. HID2 Field Descriptions (continued)
Bits Name Function