Freescale Semiconductor MPC8260 - Manual (Page 128)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-10 Freescale Semiconductor
Figure 2-2. PowerQUICC II Programming Model—Registers
DSISR
SPR 18 DSISR
Data Address Register
SPR 19 DAR
SPR 26 SRR0
SPR 27 SRR1
SPRGs
SPR 272 SPRG0
SPR 273 SPRG1
SPR 274 SPRG2
SPR 275 SPRG3
Exception Handling Registers
Save and Restore Registers
Instruction BAT
Registers
SPR 528 IBAT0U
SPR 529 IBAT0L
SPR 530 IBAT1U
SPR 531 IBAT1L
SPR 532 IBAT2U
SPR 533 IBAT2L
SPR 534 IBAT3U
SPR 535 IBAT3L
Data BAT Registers
SPR 536 DBAT0U
SPR 537 DBAT0L
SPR 538 DBAT1U
SPR 539 DBAT1L
SPR 540 DBAT2U
SPR 541 DBAT2L
SPR 542 DBAT3U
SPR 543 DBAT3L
Memory Management Registers
Software Table
Search Registers
1
SPR 976 DMISS
SPR 977 DCMP
SPR 978 HASH1
SPR 979 HASH2
SPR 980 IMISS
SPR 981 ICMP
SPR 982 RPA
Machine State
Register
MSR
Processor Version
Register
SPR 287 PVR
Configuration Registers
Hardware
Implementation
Registers
1
SPR HID0
TBR 268 TBL
TBR 269 TBU
SPR 1
USER MODEL
UISA
Condition Register
GPR0
GPR1
GPR31
General-Purpose
Registers
Floating-Point
Registers
XER
XER
SPR 8
Link Register
LR
Time Base Facility
(For Reading)
SUPERVISOR MODEL—OEA
SPR 22
Decrementer
DEC
Time Base Facility
(For Writing)
SPR 284 TBL
SPR 285 TBU
SPR 282
External Address
Register (Optional)
EAR
SDR1
SPR 25 SDR1
SPR 9
Count Register
CTR
Miscellaneous Registers
SPR IABR
Instruction Address
Breakpoint Register
1
Segment Registers
SR0
SR1
SR15
FPR0
FPR1
FPR31
1
These implementation–specific registers may not be supported by other processors or processor cores.
SPR HID1
CR
.
USER MODEL
VEA
SPR HID2