10 mcc initialization and start/stop sequence, Mcc initialization and start/stop sequence -47 – Freescale Semiconductor MPC8260 User Manual
Page 895
Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
28-47
The data length and buffer pointer are described below:
•
Data length. The data length is the number of bytes the MCC should transmit from this BD’s data
buffer. It is never modified by the CP. The value of this field should be greater than zero.
•
Tx buffer pointer. The transmit buffer pointer, which contains the address of the associated data
buffer, may be even or odd provided that SS7_OPT[SEN_FIS] = 0 (refer to
Configuration Register—SS7 Mode”
). If the automatic FISU option is required, the buffer pointer
must be 4-byte aligned. The buffer must reside in external memory. This value is never modified
by the CP.
28.10 MCC Initialization and Start/Stop Sequence
The MCC must be initialized and started/stopped in relation with the corresponding TDMs. The following
section presents the initialization and start/stop sequences which must be followed for single and super
channels.
The following is a general sequence for initializing an MCC and its channels after reset:
1. Program the parallel I/O port interface for the TDM to be used (refer to
).
2. Program the SIU’s interrupt controller to mask or enable MCC-related interrupts as desired (refer
Section 4.3.1, “Interrupt Controller Registers”
).
8
UB
User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this
bit is used.
9–10
—
Reserved, should be cleared.
11
—
Reserved, should be cleared.
SUD
SS7 mode only: Signal unit delay
0 This buffer does not have a transmission delay.
1 A time delay of JTTDelay
x
512 µs passes before this buffer is transmitted. Can be used for LSSU
transmission according to the JT Q.703 Standard which defines a 24 ms delay between
back-to-back LSSUs. This bit is only valid when SS7_OPT[STD] is set.
12–15
PAD
Pad characters. These four bits indicate the number of PAD characters (0x7E or 0xFF depending on
the IDLM mode selected in the CHAMR register) that the transmitter sends after the closing flag.
The transmitter issues a TXB interrupt only after sending the programmed number of pads to the Tx
FIFO buffer. The user can use the PAD value to guarantee that the TXB interrupt occurs after the
closing flag has been sent out on the TXD line. PAD = 0, means that the TXB interrupt is issued
immediately after the closing flag is sent to the Tx FIFO buffer. The number of PAD characters
depends on the FIFO size assigned to the channel in the MCC hardware. If the channel is not part
of a super channel then the MCC hardware assigns to this channel a fifo of 4 bytes. So in this case
a pad of 4 bytes ensures that the TXB interrupt is not given before the closing flag has been
transmitted over the TXD line. For a super channel, the FIFO length equals the number of time slots
assigned to the super channel multiplied by two.
Table 28-23. TxBD Field Descriptions (continued)
Bits
Name
Description