Freescale Semiconductor MPC8260 - Manual (Page 368)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-62 Freescale Semiconductor
9.11.2.26 PCI Configuration Register Access from the Core
The 60x bus master cannot directly access the PCI configuration registers because they are not in the
internal memory-mapped configuration register’s space. The 60x bus master must first load CFG_ADDR
(at offset 0x10900 in the memory-mapped configuration registers block) with a 32-bit register address in
the form ‘0x8000_0nnn,’ where nnn is the address offset of the desired PCI configuration register. The data
can then be accessed in CFG_DATA (at offset 0x10904 in the internal memory map). See
Section 9.9.1.4.4, “Host Mode Configuration Access.”
When accessing the PCI bridge’s PCI configuration registers with the 60x bus master, note the following:
• The bus number and device number fields of the CFG_ADDR register should be cleared.
• Accesses to CFG_ADDR or CFG_DATA which are greater than 4 bytes generate an illegal register
access error setting ECR[IRA]; see
Section 9.11.1.11, “Error Control Register (ECR).”
• Accesses to CFG_DATA without a valid offset in CFG_ADDR generates an I/O transaction
on the PCI bus.
9.11.2.27 PCI Configuration Register Access in Big-Endian Mode
Since the local CPU (internal core or external) is operating in big-endian mode, software must byte-swap
the data of the configuration register before performing an access. That is, the data appears in the core
register in ascending significance byte order (LSB to MSB). Software loads the configuration register
address and the configuration register data into the core register in ascending significance byte order (LSB
to MSB).
Note that in the following examples, the data in the configuration register (at 0x18) is shown in
little-endian order. This is because all the internal registers are intrinsically little-endian.
Example: configuration sequence, 2-byte data write to register at address offset 0x1A for PCI bus.
Initial values:
r0 contains 0x1800_0080
r1 contains IMMR+0x10900
r2 contains IMMR+0x10904
r3 contains 0xDDCC_BBAA
Register at 0x18 contains 0xFFFF_FFFF (1B to 18)
Code sequence:
stw r0,0(r1)
sth r3,2(r2)
Results: Address IMMR+0x10900 contains 0x8000_0018 (MSB to LSB)
Address IMMR+0x10904 contains 0xXXXX_AABB (MSB to LSB) where ‘XXXX’ is
the old value and is not affected the sth.
Note: the address of PCI_CFG_DATA must match the offset address 0x1A.
Register at 0x18 contains 0xAABB_FFFF (1B to 18)
This example shows an address of IMMR+0x10906 used to access the PCI_CFG_DATA. This was done
in order to align the data with the address 0x1A. The address used to access PCI_CFG_DATA can have a
value of IMMR+0x10904, IMMR+0x10905, IMMR+0x10906, or IMMR+0x10907. The two least
significant bits of the address used to access PCI_CFG_DATA should match the byte-wise offset of the
register being accessed. For instance, if 0x0D is the offset of the register being accessed, then the address
used to access PCI_CFG_DATA must be IMMR+0x10905.