Freescale Semiconductor MPC8260 - Manual (Page 873)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 28-25
28.3.4.3.1 AERM Implementation
The SS7 microcode implements the ITU Q.703 alignment error rate monitor (AERM). The microcode uses
the T, SUERM, M and M_cnt parameters. The M_cnt parameter is incremented for every T errored frames.
If M_cnt reaches M, an AERM interrupt is generated to layer 3.
Note that in AERM mode no SUERM interrupt is generated. Also, the algorithm associated with D and
D_cnt is disabled as per the ITU specification.
28.3.4.3.2 AERM in Japanese SS7
To meet the Japanese AERM requirements the user must change the parameters T and D. Note that the
interrupt generated is not AERM but SUERM.
During proving, do the following:
1. Set SS7_OPT register to 0b0000 001X XX00 XXXX. The value of X doesn’t matter because these
bits do not affect the operation of the error counter.
2. Clear JTRdelay parameter to'0.'
3. Set parameters T (threshold) and D (up counter) to'1.'
4. Clear parameter SUERM (error counter) to'0.'
5. Set JTTDelay to value required to generate 24ms delay.
These settings allow FISU or LSSU transmission to be delayed by the required 24ms (JTTDelay). They
also allow the correct operation of the JT Q703 error counter and ensure that an SUERM interrupt is
generated on the first SU received in error.
After proving period, set the parameters (T and D) to values according to the Japanese SUERM. See
section
Table 28-12 .
9 SEN_FIS Send FISU if first BD of frame is not ready.
0 Flags are sent if the current BD, which is the first BD of the frame, does not have its ready bit set.
1 FISUs are automatically sent if the current BD, which is the first BD of the frame, does not have
its ready bit set.
10 O_ORN Enter octet counting mode (OCM) on overrun. Should be cleared if using the Japanese standard.
0 Disable entering OCM if there are no receive BDs available.
1 Enter OCM if there are no receive BDs available.
Note that when STD = 1, O_ORN = 1, and no receive buffers are ready, a ny received signal unit
is treated as an erred signal unit.
11 O_ITUT Enter octet counting mode (OCM) on ITU-T conditions (after an abort sequence or when an SU is
too long). Should be cleared if using the Japanese standard.
0 Disable entering OCM on ITU-T conditions.
1 Enable entering OCM on ITU-T conditions.
12-15 FISU_PAD Padding of the automatically transmitted FISUs. If the SEN_FISU bit is set, the CP will use the
value of FISU_PAD as a number of pad character. Please refer to PAD parameter in
Section 28.9.2,
“Transmit Buffer Descriptor (TxBD) .”
Table 28-13. SS7 Configuration Register Fields Description
Bits Name Description