Freescale Semiconductor MPC8260 - Manual (Page 403)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-97
Byte Count = 0x67452301 <MSB..LSB>
9.13.2.2 Descriptor in Little Endian Mode
In little endian mode, the descriptor in PCI memory should be programmed such that data appears in
descending significant byte order. If segment descriptors are written to memory located in the PCI bus,
they are obeying the rules for little endian mode.
Example: Little Endian mode descriptor’s data structure. Note that the descriptor structure must be
aligned on an 8-word boundary.
struct {
double a; /* 0x8877665544332211 double word */
double b; /* 0x1122334488776655 double word */
double c; /* 0x7654321012345678 double word */
double d; /* 0x0123456776543210 double word */
} Descriptor;
Results: Source Address = 0x44332211 <MSB..LSB>
Destination Address = 0x88776655 <MSB..LSB>
Next Descriptor Address = 0x12345678 <MSB..LSB>
Byte Count = 0x76543210 <MSB..LSB>
9.14 Error Handling
The PCI bridge provides error detection and reporting. This section describes how the PCI bridge handles
different error (or interrupt) conditions.
Errors detected by the PCI bridge are reported by asserting internal error signals for each detected error.
The system error (SERR) and parity error (PERR) signals are used to report errors on the PCI bus.
The PCI command and status registers and the error handling registers enable or disable the reporting and
detection of specific errors. There are six registers which define capture and control functionality under
error conditions. Refer to section 9.11.1.9 through section 9.11.1.14.
The PCI bridge detects illegal transfer sizes to its configuration registers, PCI master-abort cycles, PCI
received target-abort errors, PCI parity errors, and overflow/underflow errors in the message unit.The PCI
bridge latches the address and type of transaction that caused the error in the error registers to assist
diagnostic and error handling software.
9.14.1 Interrupt and Error Signals
Although Section 9.11, “Configuration Registers,” contains the definitions for the interrupt and error
signals, this section describes the interactions between system components when an interrupt or error
signal is asserted.
9.14.1.1 PCI Bus Error Signals
The PCI bridge uses two error signals to interact with the PCI bus, SERR and PERR.