Freescale Semiconductor MPC8260 - Manual (Page 412)

Clocks and Power Control
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
10-6 Freescale Semiconductor
10.7 PLL Pins
Table 10-1 shows dedicated PLL pins.
Table 10-1. Dedicated PLL Pins
Signal Description
VCCSYN
1
Drain voltage—Analog VDD dedicated to core analog PLL circuits. To ensure core clock stability, filter the
power to the VCCSYN1 input with a circuit similar to the one in
Figure 10-4 . To filter as much noise as
possible, place the circuit as close as possible to VCCSYN1. The 0.1-µF capacitor should be closest to
VCCSYN1, followed by the 10-µF capacitor, and finally the 10-
Ω resistor to Vdd. These traces should be
kept short and direct.
VCCSYN Drain voltage—Analog VDD dedicated to analog main PLL circuits. To ensure internal clock stability, filter
the power to the VCCSYN input with a circuit similar to the one in Figure 10-4 . To filter as much noise as
possible, place the circuit should as close as possible to VCCSYN. The 0.1-µF capacitor should be closest
to VCCSYN, followed by the 10-µF capacitor, and finally the 10-
Ω resistor to Vdd. These traces should be
kept short and direct.
GNDSYN Source voltage—Analog VSS dedicated to analog main PLL circuits. Should be provided with an
extremely low impedance path to ground and should be bypassed to VCCSYN by a 0.1-µF capacitor
located as close as possible to the chip package. The user should also bypass GNDSYN to VCCSYN with
a 0.01-µF capacitor as close as possible to the chip package.