Freescale Semiconductor MPC8260 - Manual (Page 1151)

Inverse Multiplexing for ATM (IMA)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 33-49
33.4.6.2 Delay Compensation Buffers (DCB)
Cells received on a link are initially stored in a delay compensation buffer (DCB). DCBs are allocated on
a per-link basis. They are of user-definable length, thereby providing a programmable maximum
synchronizable delay. Note that DCBs of links within a group must all have the same size.
DCBs consist of a circular queue of 64-byte cell buffers. These cell buffers contain the received cell
followed by 12 bytes of header/status information.
Figure 33-27. Cell Buffer in Delay Compensation Buffer
The length of a DCB is defined by the link’s DCBSP and DCBEP parameters. The length of the DCB
(defined by (DCBEP-DCBSP)
x 16) must be an integer multiple of the IMA frame length in bytes, M x 64.
Furthermore, the DCBSP must be aligned on a M x 64-byte boundary. For example, if M = 64, then DCBSP
must be on a 4KB boundary. To ensure group delay synchronization, the minimum length of the DCB
should be 2(Mx64).
The DCB memory area must be initialized to zero at link startup.
Figure 33-28. IMA Delay Compensation Buffer
33.4.7 IMA Exceptions
One of the four ATM interrupt queues must be dedicated to IMA events. This enables minimum latency
in dealing with the IMA state machines, and ensures that the unique format for IMA exceptions are not
confused with other exceptions. The IMA interrupt queue is defined in the IMACNTL[INTQ] parameter.
64 bytes
12 bytes HEADER/STATUS
52 bytes RX CELL
IMA External Structure Region
DCB
IMAEXTBASE DCBSP
bits 0-11 bits12-27
0000
bits 28-31
IMAEXTBASE DCBEP 0000
IMAEXTBASE
M x 64-byte boundary
(DCBEP - DCBSP) x 16