4 address transfer termination, 1 address retried with artry, Address transfer termination -22 – Freescale Semiconductor MPC8260 User Manual
Page 296: Address retried with artry -22
The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-22
Freescale Semiconductor
Extended transfer mode is enabled by setting the BCR[ETM].
8.4.4
Address Transfer Termination
Address transfer termination occurs with the assertion of the address acknowledge (AACK) signal, or
retried with the assertion of ARTRY. ARTRY must remain asserted until one clock after AACK; the bus
clock cycle after AACK is called the ARTRY window. The PowerQUICC II controls assertion of AACK
unless the cycle is claimed by an external slave, such as an external L2 cache controller. Following the
assertion of L2_HIT, the L2 cache controller is responsible for asserting AACK. When AACK is asserted
by the external slave, it should be asserted for one clock cycle and then negated for one clock cycle before
entering a high-impedance state. The PowerQUICC II holds AACK in a high-impedance state until it is
required to assert AACK to terminate the address cycle.
The PowerQUICC II uses AACK to enforce a pipeline depth of one to its internal slaves.
8.4.4.1
Address Retried with ARTRY
The address transfer can be terminated with the requirement to retry if ARTRY is asserted during the
address tenure and through the cycle following AACK. The assertion causes the entire transaction (address
and data tenure) to be rerun. As a snooping device, the PowerQUICC II processor asserts ARTRY for a
snooped transaction that hits modified data in the data cache that must be written back to memory, or if the
snooped transaction could not be serviced. As a bus master, the PowerQUICC II responds to an assertion
of ARTRY by aborting the bus transaction and requesting the bus again, as shown in
. Note that
after recognizing an assertion of ARTRY and aborting the current transaction, the PowerQUICC II may
not run the same transaction the next time it is granted the bus.
7-Byte
x
x
0
0
0
Byte
6-Byte
x
x
0
0
1
x
x
0
0
1
x
x
0
1
0
x
x
0
0
0
Half
5-Byte
x
x
0
1
0
x
x
0
0
1
6-Byte
x
x
0
1
0
x
x
0
0
0
Word
3-Byte
x
x
1
0
0
x
x
0
0
1
4-Byte
x
x
1
0
0
x
x
x
x
x
Double
Stop
Table 8-12. Address and Size State for Extended Transfers (continued)
Size State [0–3]
Address State[0–4]
Port Size
Next Size State [0–3]
Next Address State[0–4]