5 set timer command, 6 risc timer initialization sequence, Set timer command -25 – Freescale Semiconductor MPC8260 User Manual
Page 573: Risc timer initialization sequence -25, Command
Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
14-25
14.6.5
SET
TIMER
Command
The
SET
TIMER
command is used to enable, disable, and configure the 16 timers in the RISC timer table
and is issued to the CPCR. This means the value 0x29E1008 should be written to CPCR. However, before
writing this value, the user should program the TM_CMD fields. See
14.6.6
RISC Timer Initialization Sequence
The following sequence initializes the RISC timers:
1. Configure RCCR to determine the preferred tick interval for the entire timer table. The TIME bit
is normally set at this time but can be set later if all RISC timers need to be synchronized.
2. Determine the maximum number of timers to be located in the timer table. Configure the
TM_BASE in the RISC timer table parameter RAM to point to a location in the dual-port RAM
with 4
× n bytes available, where n is the number of timers. If n is less than 16, use timer 0 through
timer n–1 to save space.
3. Clear the TM_CNT field in the RISC timer table parameter RAM to show how many ticks elapsed
since the RISC internal timer was enabled. This step is optional.
4. Clear RTER, if it is not already cleared. Write ones to clear this register.
5. Configure RTMR to enable the timers that should generate interrupts. Ones enable interrupts.
6. Set the RISC timer table bit in the SIU interrupt mask register (SIMR_L[RTT]) to generate
interrupts to the system. The SIU interrupt controller may require other initialization not mentioned
here.
7. Configure the TM_CMD field of the RISC timer table parameter RAM. At this point, determine
whether a timer is to be enabled or disabled, one-shot or restart, and what its timeout period should
be. If the timer is being disabled, the parameters (other than the timer number) are ignored.
8. Issue the
SET
TIMER
command by writing 0x29E1_0008 to the CPCR.
9. Repeat the preceding two steps for each timer to be enabled or disabled.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field TMR
15
TMR
14
TMR
13
TMR
12
TMR
11
TMR
10
TMR
9
TMR
8
TMR
7
TMR
6
TMR
5
TMR
4
TMR
3
TMR
2
TMR
1
TMR
0
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x0x119D6 (RTER)/0x0x119DA (RTMR)
Figure 14-11. RISC Timer Event Register (RTER)/Mask Register (RTMR)