Freescale Semiconductor MPC8260 - Manual (Page 306)

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-32 Freescale Semiconductor
8.7.1 Support for the lwarx/stwcx. Instruction Pair
The load word and reserve indexed (lwarx) and the store word conditional indexed (stwcx.) instructions
provide a way to update memory atomically by setting a reservation on the load and checking that the
reservation is still valid before the store is performed. In the PowerQUICC II, reservations are made on
behalf of aligned, 32-byte sections of the memory address space.
The reservation (RSRV) output signal is driven synchronously with the bus clock and reflects the status of
the reservation coherency bit in the reservation address register.
Note that each external master must do its own snooping; the PowerQUICC II does not provide external
reservation snooping.
8.7.2 TLBISYNC Input
The TLBISYNC input permits hardware synchronization of changes to MMU tables when the
PowerQUICC II and another DMA master share the MMU translation tables in system memory. A DMA
master asserts TLBISYNC when it uses shared addresses that the PowerQUICC II could change in the
MMU tables during the DMA master’s tenure.
When the TLBISYNC input is asserted, the PowerQUICC II cannot complete any instructions past a
tlbsync instruction. Generally, during the execution of an eciwx or ecowx instruction, the selected DMA
device should assert the PowerQUICC II’s TLBISYNC signal and hold it asserted during its DMA tenure
if it is using a shared translation address. Subsequent instructions by the PowerQUICC II processor should
include a sync and tlbsync instruction before any MMU table changes are performed. This prevents the
PowerQUICC II from making disruptive table changes during the DMA tenure.
8.8 Little-Endian Mode
The PowerQUICC II supports a little-endian mode in which low-order address bits are operated on
(munged) based on the size of the requested data transfer. This mode allows a little-endian program
running on the processor with a big-endian memory system to offset into a data structure and receive the
same results as it would if it were operating on a true little-endian processor and memory system. For
example, writing a word to memory as a word operation on the bus and then reading in the second byte of
that word as a byte operation on the bus.
NOTE
When the processor is selected for little-endian operation, the bus interface
is still operating in big-endian mode. That is, byte address 0 of a double
word (as selected by A[29–31] on the bus—after the internal address
munge) still selects the most significant (left most) byte of the double word
on D[0–7]. If the processor interfaces with a true little-endian environment,
the system may need to perform byte-lane swapping or other operations
external to the processor.