Freescale Semiconductor MPC8260 - Manual (Page 986)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
30-66 Freescale Semiconductor
Table 30-31 describes control slot fields.
30.10.5 ATM Controller Buffer Descriptors (BDs)
Each ATM channel has separate receive and transmit BD tables. The number of BDs per channel and the
size of the buffers is user-defined. The last BD in each table holds a wrap indication. Each BD in the TxBD
table points to a buffer to send. At the receive side, the user can choose one of two modes:
• Static buffer allocation. In this mode, the user allocates dedicated buffers to each ATM channel
(that is, the user associates each BD with one buffer). Static buffer allocation is useful when the
connection rate is known and constant and when data must be reassembled in a particular memory
space.
• Global buffer allocation. Available for AAL5 only. In this mode, buffer allocation is dynamic. The
user allocates receive buffers and places them in global buffer pools. When the CP needs a receive
buffer, it first fetches a buffer pointer from one of the global buffer pools and writes the pointer to
the current RxBD. Global buffer allocation is optimized for allocating memory among many ATM
channels with variable data rates, such as ABR channels.
30.10.5.1 Transmit Buffer Operation
The user prepares a table of BDs pointing to the buffers to be sent. The address of the first BD is put in the
channel’s TCT[TBD_BASE]. The transmit process starts when the core issues an
ATM TRANSMIT
command. The CP reads the first TxBD in the table and sends its associated buffer. When the current buffer
is finished, the CP increments TBD_Offset, which holds the offset from TBD_BASE to the current BD. It
then reads the next BD in the table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the
current BD is not ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which
case the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a new
ATM
TRANSMIT command to restart transmission.
Figure 30-41 shows the ready bit in the TxBD tables and their associated buffers for two example ATM
channels.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field TCTE 000_0000_0000_0000
Figure 30-40. Control Slot
Table 30-31. Control Slot Field Description
Bits Name Description
0 TCTE Used for external channels only.
0 Channels in this scheduling table do not use external TCTE. (No external VBR, ABR, UBR+
channels)
1 Channels in this scheduling table use external TCTE. (External VBR, ABR, UBR+ channels)
1–15 — Reserved, should be cleared.