Freescale Semiconductor MPC8260 - Manual (Page 410)

Clocks and Power Control
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
10-4 Freescale Semiconductor
Figure 10-2. PCI Bridge as an Agent, Operating from the PCI System Clock
10.4.3.2 PCI Bridge as a Host and Generating the PCI System Clock
In a system where the PowerQUICC II is the host that generates the PCI clock, the 60x bus clock should
be driven to the CLKIN1 pin. The 60x bus clock is internally multiplied by the PLL to generate the CPM
high speed clock and then internally divided for generating the PCI bus clock. The PCI bus clock is then
driven by the DLL circuit to the DLLOUT pin, which has a feedback path from the board to the CLKIN2
pin. This feedback is used to control the clock skew in order to have the same internal and external clock
timing.
NOTE
All PCI timings are measured relative to CLKIN2, and all 60x bus timings
are measured relative to CLKIN1.
Figure 10-3. PCI Bridge as a Host, Generating the PCI System Clock
PLL
Divider
PCI Interface
%
%
cpm_clk
bus_clk
pci_clk
60x Circuit
PCI Circuit
clkin1
dllout
clkin2
PCI Clock Bus Clock
PowerQUICC II
bus_clk
DLL
PLL
Divider
PCI Interface
%
%
cpm_clk
bus_clk
pci_clk
PCI Circuit
60x Circuit
clkin1
dllout
clkin2
60x Bus Clock PCI Clock
PowerQUICC II
pci_clk
DLL