Freescale Semiconductor MPC8260 - Manual (Page 212)

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-40 Freescale Semiconductor
4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
The 60x bus transfer error status and control register 2 (TESCR2) is shown in Figure 4-32 .
7–9 TC Transfer code. Indicates the transfer code of the 60x bus transaction that caused the TEA or MCP.
See
Section 8.4.3.2, “Transfer Code Signals TC[0–2],” for a description of the various transfer
codes.
10 — Reserved, should be cleared.
11–15 TT Transfer type. These bits indicates the transfer type of the 60x bus transaction that caused the TEA
or MCP. See
Section 8.4.3.1, “Transfer Type Signal (TT[0–4]) Encoding,” for a description of the
various transfer types.
16 — Reserved, should be cleared.
17 DMD Data errors disable.
0 Errors are enabled.
1 All data errors (parity and single and double ECC errors) on the 60x bus are disabled.
18 — Reserved, should be cleared.
19 — All non-PCI devices: Reserved, should be cleared.
PCIMCP MPC8250, MPC8265, and MPC8266 only: PCI machine check. Set when a core machine check is
asserted from the PCI bridge.
20 — .29
µm (HiP3) Rev A.1 devices: Reserved, should be cleared.
DER .29
µm (HiP3) Rev B.3 silicon and forward: Data error. Set when a core machine check is asserted
due to ECC or parity errors.
21 — .29 µm (HiP3) Rev A.devices: Reserved, should be cleared.
IRQ0 .29 µm (HiP3) Rev B.3 silicon and forward: External machine check. Set when a machine check is
asserted due to the external machine check pin (IRQ0).
22 — .29 µm (HiP3) Rev A.1 devices: Reserved, should be cleared.
SWD .29 µm (HiP3) Rev B.3 silicon and forward: Software watchdog time-out. Indicates that a core
machine check was asserted due to a time-out in the software watchdog. See Section 4.1.5,
“Software Watchdog Timer.”
23 — .29 µm (HiP3) Rev A.1 devices: Reserved, should be cleared.
ADO .29 µm (HiP3) Rev B.3 silicon and forward: 60x bus monitor address-only time-out. Set when a core
machine check is asserted due to time-out of the bus monitor in an address only transaction. See
Section 4.1.1, “Bus Monitor.”
24–31 ECNT Single ECC error counter. Indicates the number of single ECC errors that occurred in the system.
When the counter reaches its maximum value (255), MCP is asserted for all single ECC errors. This
feature gives the system the ability to withstand a few random errors yet react to a catastrophic
failure. The user can set a lower threshold to the number of tolerated single ECC errors by writing
some value to ECNT. The counter starts from this value instead of zero.
Table 4-15. TESCR1 Field Descriptions (continued)
Bits Name Description