Freescale Semiconductor MPC8260 - Manual (Page 1128)

Inverse Multiplexing for ATM (IMA)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
33-26 Freescale Semiconductor
33.4.2 IMA FCC Programming
33.4.2.1 FCC Registers
33.4.2.1.1 FPSMRx
The FCC protocol-specific mode register (FPSMR) for ATM operation is described in Section 30.13.2,
“FCC Protocol-Specific Mode Register (FPSMR).” Refer to that section for information pertaining to
IMA.
33.4.2.1.2 FTIRRx
For any PHY programmed in IMA mode (i.e. corresponding bit in IMAPHY is set), the corresponding
FTIRRx must be programmed to zero, for external rate mode. However, for PHYs 0-3, internal rate mode
may be selected for non-IMA PHYs. Refer to
Section 30.13.4, “FCC Transmit Internal Rate Registers
(FTIRRx) (FCC1 and FCC2 Only).”
33.4.2.2 FCC Parameters
33.4.2.2.1 TCELL_TMP_BASE and RCELL_TMP_BASE
The TCELL_TMP_BASE and RCELL_TMP_BASE have the same definitions as for a standard FCC, in
that they contain 64-byte aligned addresses of regions of DPRAM for temporary cell storage. However,
the 4 bytes leading and 4 bytes following the region indicated by TCELL_TMP_BASE must also be
reserved for use by the IMA microcode (thereby increasing its size to 60 bytes); and the 12 bytes following
the region indicated by RCELL_TMP_BASE must also be reserve for use by the IMA microcode (thereby
increasing its size to 64 bytes).
RCELL_TMP_BASE may be programmed to any 64-byte aligned address. TCELL_TMP_BASE must be
programmed to a 64-byte aligned address terminating with 0x40 (i.e. 0xnn40).
33.4.2.2.2 GMODE
IMA functionality in ROM is enabled using the GMODE register. Refer to Section 30.10.1.3, “Global
Mode Entry (GMODE).”
33.4.2.3 IMA-Specific FCC Parameters
The following parameter must be programmed in the FCC parameter RAM page in addition to the standard
FCC parameters for ATM.
Table 33-2. FCC Parameter RAM Additions
Offset Name Width Description
0xEE IMAROOT Hword Offset of IMA root table in DPRAM. Must be 128-byte aligned.