Freescale Semiconductor MPC8260 - Manual (Page 202)

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-30 Freescale Semiconductor
4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
The 60x bus arbitration-level registers, shown in Figure 4-23 and Figure 4-24 , define arbitration priority
of PowerQUICC II bus masters. Priority field 0 has highest-priority. For information about
PowerQUICC II bus master indexes, see the description of PPC_ACR[PRKM] in
Table 4-10 .
Table 4-10. PPC_ACR Field Descriptions
Bits Name Description
0–1 — Reserved, should be cleared.
2 DBGD Data bus grant delay. Specifies the minimum number of data tenure wait states for 60x bus
master-initiated data operations. This is the minimum delay between TS and DBG.
0 DBG is asserted with TS if the data bus is free.
1 DBG is asserted one cycle after TS if the data bus is not busy.
See
Section 8.5.1, “Data Bus Arbitration.”
3 EARB External arbitration.
0 Internal arbitration is performed. See
Section 8.3.1, “Arbitration Phase.”
1 External arbitration is assumed.
4–7 PRKM Parking master.
0000 CPM high request level refers to the IDMA which involves peripherals and the following serial
channels (SCC, SPI, SMC, and I
2
C)
0001 CPM middle request level refers to all other serial channels (FCCs and MCCs)
0010 CPM low request level: it is possible to change the request level for all FCCs and MCCs to low
priority when PPC_ACR[4–7] = 0010 and FCRx[1] = 1 (See Section 29.7.1, “FCC Function
Code Registers (FCRx).”
0011 PCI request level (MPC8250, MPC8265, and MPC8266 only). Reserved on all other devices.
0100 Reserved
0101 Reserved
0110 Internal core
0111 External master 1
1000 External master 2
1001 External master 3
Values 1010–1111 are reserved.
0 3 4 7 8 11 12 15
Field Priority Field 0 Priority Field 1 Priority Field 2 Priority Field 3
Reset 0000 0001 0010 0110
R/W R/W
Addr 0x0x1002C
16 19 20 23 24 27 28 31
Field Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7
Reset 0011 0100 0101 0111
R/W R/W
Addr 0x1002E
Figure 4-23. PPC_ALRH