Freescale Semiconductor MPC8260 - Manual (Page 800)

SCC Ethernet Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
25-16 Freescale Semiconductor
25.18 SCC Ethernet Receive BD
The Ethernet controller uses the RxBD to report on the received data for each buffer.
Table 25-7 describes RxBD status and control fields.
12–14 NIB Number of ignored bits. Determines how soon after RENA assertion the Ethernet controller should
begin looking for the start frame delimiter. Typically NIB = 101 (22 bits).
000 Begin searching 13 bits after the assertion of RENA.
001 Begin searching 14 bits after the assertion of RENA.
...
111 Begin searching 24 bits after the assertion of RENA.
15 FDE Full duplex Ethernet.
0 Disable full-duplex Ethernet mode.
1 Enable full-duplex Ethernet mode.
Note: When FDE = 1, PSMR[LPB] must be set also.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E — W I L F — M — LG NO SH CR OV CL
Offset + 2 Data Length
Offset + 4 Rx Data Buffer Pointer
Offset + 6
Figure 25-6. SCC Ethernet RxBD
Table 25-7. SCC Ethernet RxBD Status and Control Field Descriptions
Bits Name Description
0 E Empty.
0 The buffer is full or stopped receiving data because an error occurred. The core can read or write
any fields of this RxBD. The CPM does not use this BD as long as the E bit is zero.
1 The buffer is not full. The CPM controls this BD and its buffer; do not modify this BD.
1 — Reserved, should be cleared.
2 W Wrap (final BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the first BD
that RBASE points to. The number of BDs is determined only by the W bit and overall space
constraints of the dual-port RAM.
3 I Interrupt. Note that this bit does not mask SCCE[RXF] interrupts.
0 No SCCE[RXB] interrupt is generated after this buffer is used.
1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the Ethernet controller. These two
bits can cause interrupts if they are enabled.
Table 25-6. PSMR Field Descriptions
Bits Name Description