Freescale Semiconductor MPC8260 - Manual (Page 476)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-58 Freescale Semiconductor
Figure 11-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)
11.5.1.4 Output Enable (OE) Timing
The timing of the OE is affected only by TRLX. It always asserts and negates on the rising edge of the
external bus clock. OE always asserts on the rising clock edge after CS is asserted, and therefore its
assertion can be delayed (along with the assertion of CS) by programming TRLX = 1. OE deasserts on the
rising clock edge coinciding with or immediately after CS deassertion.
11.5.1.5 Programmable Wait State Configuration
The GPCM supports internal PSDVAL generation. It allows fast accesses to external memory through an
internal bus master or a maximum 17-clock access by programming ORx[SCY]. The internal PSDVAL
generation mode is enabled if ORx[SETA] = 0. If GTA is asserted externally at least two clock cycles
before the wait state counter has expired, the current memory cycle is terminated. When TRLX = 1, the
number of wait states inserted by the memory controller is defined by 2 x SCY or a maximum of 30 wait
states.
Clock
Address
PSDVAL
CS
BCTL x
WE
OE
Data