Freescale Semiconductor MPC8260 - Manual (Page 921)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-1
Chapter 30
ATM Controller and
AAL0, AAL1, and AAL5
NOTE
The functionality described in this chapter is not available on the MPC8250.
The ATM controller provides the ATM and AAL layers of the ATM protocol using the universal test and
operations physical layer (PHY) interface for ATM (UTOPIA level II) for both master and slave modes. It
performs segmentation and reassembly (SAR) functions of AAL5, AAL1 circuit emulation service (CES),
AAL2, and AAL0, and most of the common parts of the convergence sublayer (CP-CS) of these protocols.
For each virtual channel (VC), the controller’s ATM pace control (APC) unit generates a cell transmission
rate to implement constant bit rate (CBR), variable bit rate (VBR), available bit rate (ABR), unspecified
bit rate (UBR) or UBR+ traffic. To regulate VBR traffic, the APC unit performs a continuous-state leaky
bucket algorithm. The APC unit also uses up to eight priority levels to prioritize real-time ATM channels,
such as CBR and real-time VBR, over non-real-time ATM channels such as VBR, ABR and UBR.
The ATM controller performs the ATM Forum (UNI-4.0) ABR flow control. To perform feedback rate
adaptation, it supports forward and backward resource management (RM) cell generation and ATM Forum
floating-point calculation. ABR flow control is implemented in hardware and firmware (without software
intervention) to prevent potential delays during backward RM cell processing and feedback rate
adaptation.
The PowerQUICC II supports a special mode for ATM/TDM interworking. The CPM performs automatic
data forwarding between ATM channels and the MCCs’ TDM channels without core intervention.
The PowerQUICC II ATM SAR controller applications are as follows:
• ATM line card controllers
• ATM-to-WAN interworking (frame relay, T1/E1 circuit emulation)
• Residential broadband network interface units (NIU) (ATM-to-Ethernet)
• High-performance ATM network interface cards (NIC)
• Bridges and routers with ATM interface
30.1 Features
The ATM controller has the following features:
• Full duplex segmentation and reassembly at 155 Mbps
• UTOPIA level II master and slave modes 8/16 bit
• AAL5, AAL1, AAL2, AAL0 protocols