Freescale Semiconductor MPC8260 - Manual (Page 138)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-20 Freescale Semiconductor
tenures of a read operation). Because the processor can dynamically optimize run-time ordering of
load/store traffic, overall performance is improved.
2.4.2.2 Instruction Cache
The instruction cache also consists of 128 sets of four blocks, and each block consists of 32 bytes, an
address tag, and a valid bit. The instruction cache may not be written to except through a block fill
operation caused by a cache miss. In the processor core, internal access to the instruction cache is blocked
only until the critical load completes.
The processor core supports instruction fetching from other instruction cache lines following the
forwarding of the critical first double word of a cache line load operation. The processor core’s instruction
cache is blocked only until the critical load completes (hits under reloads allowed). Successive instruction
fetches from the cache line being loaded are forwarded, and accesses to other instruction cache lines can
proceed during the cache line load operation.
The instruction cache is not snooped, and cache coherency must be maintained by software. A fast
hardware invalidation capability is provided to support cache maintenance. The organization of the
instruction cache is very similar to the data cache shown in
Figure 2-6 .
2.4.2.3 Cache Locking
The processor core supports cache locking, which is the ability to prevent some or all of a microprocessor’s
instruction or data cache from being overwritten. Cache entries can be locked for either an entire cache or
for individual ways within the cache. Entire data cache locking is enabled by setting HID0[DLOCK], and
entire instruction cache locking is enabled by setting HID0[ILOCK]. For more information, refer to Cache
Locking on the G2 Core application note (order number: AN1767/D). Cache way locking is controlled by
the IWLCK and DWLCK bits of HID2.
2.4.2.3.1 Entire Cache Locking
When an entire cache is locked, hits within the cache are supplied in the same manner as hits to an
unlocked cache. Any access that misses in the cache is treated as a cache-inhibited access. Cache entries
that are invalid at the time of locking will remain invalid and inaccessible until the cache is unlocked. Once
the cache has been unlocked, all entries (including invalid entries) are available. Entire cache locking is
inefficient if the number of instructions or the size of data to be locked is small compared to the cache size.
2.4.2.3.2 Way Locking
Locking only a portion of the cache is accomplished by locking ways within the cache. Locking always
begins with the first way (way0) and is sequential. That is, it is valid to lock ways 0, 1, and 2 but it is not
possible to lock just way0 and way2). When using way locking at least one way must be left unlocked. The
maximum number of lockable ways is three.
Unlike entire cache locking, invalid entries in a locked way are accessible and available for data
placement. As hits to the cache fill invalid entries within a locked way, the entries become valid and
locked. This behavior differs from entire cache locking where nothing is placed in the cache, even if
invalid entries exist in the cache. Unlocked ways of the cache behave normally.