Freescale Semiconductor MPC8260 - Manual (Page 369)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-63
9.11.2.27.1 Additional Information on Endianess
The endianess of both the MPC826x's peripheral logic (GPCR[LE_MODE]—see the following section)
and the MPC826x's 603e CPU core (MSR[LE]) must be set to the same endianess configuration—that is
both must be set for little or big endian operation.
For applications where little endian (LE) devices, such as those commonly found on the PCI bus, share
memory with the MPC826x, it is recommended to leave the MPC826x's 603e core CPU and peripheral
logic in the big endian (BE) modes and then to use a region of the PowerQUICC II local memory for
LE-formatted data. When a little endian PCI device stores data to this memory region, the PowerQUICC
II internal peripheral logic (in big endian mode) stores the data into memory in LE format. Likewise, when
a little-endian PCI device reads data from this memory region, the MPC826x internal peripheral logic (in
BE mode) provides the data to the PCI device in LE format.
A little-endian PCI device can share this LE memory region with the PowerQUICC II local processor
(603e core CPU) running in big endian if, when the PowerQUICC II accesses that LE region, it uses the
lwbrx and stwbrx commands. The lwbrx command byte-swaps the LE data from that region so the 603e
CPU sees the data in BE format. Similarly, the stwbrx command byte-swaps the BE data from the 603e
processor being stored to that region of memory, so it is stored into the memory region in LE format.
For the MPC603e and the PowerQUICC II implementations, there is NO latency difference associated
with lwbrx and stwbrx commands compared to the other load and store commands.
9.11.2.27.2 Notes on GPCR[LE_MODE]
GPCR[LE_MODE] (refer to Section 9.11.1.7) determines the endianess of the PCI section of
PowerQUICC II. The default value of GPCR[LE_MODE] (offset: 0x1087C) is 0. If LE_MODE is set
while a program is executing, care should be taken as to how subsequent accesses to the PCI
memory-mapped registers are made. Consider the following two examples (assume internal memory starts
at 0x04700000):
Example 1— Accessing PCI memory-mapped registers before GPCR[LE_MODE] is set. Assume that
one wants to use CPU software to set CTM of PCI DMA0 mode register
(DMAMR0[CTM]) located at 0x04710500. The value constructed from the bit field
description of the DMAMR0 is 0x00000004. However, the value written to this register is
0x04000000—the byte-swapped version of 0x00000004.
Example 2—Accessing PCI memory-mapped registers after GPCR[LE_MODE] is set. Assume that, after
GPCR[LE_MODE] is set, one wants to use CPU software to set DMAMR0[CTM].
Because of address munging, this register is now located at 0x04710504. This new address
is derived from the following:
1.The register is located at 0x04710500.
2.For a 4-byte access, address munging dictates that the XOR value is 0b100 (refer to
Chapter 4 of the Programming Environments Manual for 32-Bit Implementations of the
PowerPC Architecture).
3.The last three bits of 0x04710500 is 0b000.
4.XOR 0b000 with 0b100 (0b000
⊕ 0b100 = 0b100).
5.Therefore, the munged address of this register would be 0x04710504.