Freescale Semiconductor MPC8260 - Manual (Page 642)

Timers
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
18-6 Freescale Semiconductor
Table 18-3 describes TMR1–TMR4 register fields.
18.2.4 Timer Reference Registers (TRR1–TRR4)
Each timer reference register (TRR1–TRR4), shown in Figure 18-6 , contains the timeout’s reference
value. The reference value is not reached until TCNx increments to equal the timeout reference value.
0 7 8 9 10 11 12 13 14 15
Field PS CE OM ORI FRR ICLK GE
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x10D90 (TMR1); 0x0x10D92 (TMR2); 0x0x10DA0 (TMR3); 0x0x10DA2 (TMR4)
Figure 18-5. Timer Mode Registers (TMR1–TMR4)
Table 18-3. TMR1–TMR4 Field Descriptions
Bits Name Description
0–7 PS Prescaler value. The prescaler is programmed to divide the clock input by values from 1 to 256. The
value 00000000 divides the clock by 1 and 11111111 divides the clock by 256.
8–9 CE Capture edge and enable interrupt.
00 Disable interrupt on capture event; capture function is disabled.
01 Capture on rising TIN
x edge only and enable interrupt on capture event.
10 Capture on falling TIN x edge only and enable interrupt on capture event.
11 Capture on any TIN x edge and enable interrupt on capture event.
10 OM Output mode
0 Active-low pulse on TOUT
x for one timer input clock cycle as defined by the ICLK bits. Thus,
TOUT x may be low for one bus clock period, one bus clock/16 period, or one TIN x clock cycle
period. TOUT x changes occur on the rising edge of the system clock.
1 Toggle TOUT x . TOUT x changes occur on the rising edge of the system clock.
11 ORI Output reference interrupt enable.
0 Disable interrupt for reference reached (does not affect interrupt on capture function).
1 Enable interrupt upon reaching the reference value.
12 FRR Free run/restart.
0 Free run. The timer count continues to increment after the reference value is reached.
1 Restart. The timer count is reset immediately after the reference value is reached.
13–14 ICLK Input clock source for the timer.
00 Internally cascaded input. For TMR1, the timer 1 input is the output of timer 2. For TMR3, the
timer 3 input is the output of timer 4. For TMR2 and TMR4, this selection means no input clock
is provided to the timer.
01 Internal bus clock.
10 Internal bus clock divided by 16.
11 Corresponding TIN
x : TIN1, TIN2, TIN3, or TIN4 (falling edge).
15 GE Gate enable.
0 TGATE
x is ignored.
1 TGATE x is used to control the timer.