Freescale Semiconductor MPC8260 - Manual (Page 1277)

I 2 C Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 39-13
Table 39-9 describes I
2
C RxBD status and control bits.
39.7.1.2 I 2 C Transmit Buffer Descriptor (TxBD)
Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The first word of the TxBD,
shown in
Figure 39-14 , contains status and control bits.
0 1 2 3 4 5 13 14 15
Offset + 0 E — W I L — OV —
Offset + 2 Data Length
Offset + 4 RX Buffer Pointer
Offset + 6
Figure 39-13. I
2
C RxBD
Table 39-9. I
2
C RxBD Status and Control Bits
Bits Name Description
0 E Empty.
0 The buffer is full or stopped receiving because of an error. The core can examine or write to any
fields of this RxBD, but the CP does not use this BD while E = 0.
1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is
set, the core should not write any fields of this RxBD.
1 — Reserved and should be cleared.
2 W Wrap (last BD in table).
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the
W bit and overall space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is full.
1 The I2CER[RXB] is set when the CP fills this buffer, indicating that the core needs to process the
buffer. The RXB bit can cause an interrupt if it is enabled.
4 L Last. The I
2
C controller sets L.
0 This buffer does not contain the last character of the message.
1 This buffer holds the last character of the message. The I
2
C controller sets L after all received
data is placed into the associated buffer, or because of a stop or start condition or an overrun.
5–13 — Reserved and should be cleared.
14 OV Overrun. Set when a receiver overrun occurs during reception. The I
2
C controller updates this bit
after the received data is placed into the associated buffer.
15 — Reserved and should be cleared.