Freescale Semiconductor MPC8260 - Manual (Page 428)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-10 Freescale Semiconductor
Note that this feature cannot be used with L2 cacheable banks and that in systems that involve both
PowerQUICC II-type masters and 60x compatible master, this feature can still be used on the 60x bus
under the following restrictions:
1. The arbiter and the memory controller are in the same PowerQUICC II.
2. The register field BCR[NPQM] is setup correctly.
See “ Section 11.9, “External Master Support (60x-Compatible Mode)” and “ Section 4.3.2.1, “Bus
Configuration Register (BCR).”
11.2.10 External Memory Controller Support
The PowerQUICC II has an option to allocate specific banks (address spaces) to be controlled by an
external memory controller or bus slave, while retaining all the bank properties: port size, data
check/correction, atomic operation, and data pipelining. This is done by programming BRx and ORx[AM]
and by setting the external memory controller bit, BRx[EMEMC]. This action automatically assigns the
bank to the 60x bus. For an access that hits the bank, all bus acknowledgment signals (such as AACK,
PSDVAL, and TA) and the memory-device control strobes are driven by an external memory controller or
slave. If the device that initiates the transaction is internal to the PowerQUICC II, the memory controller
handles the port size, data checking, atomic locking, and data pipelining as if the access were governed by
it.
This feature allows multiple PowerQUICC II systems to be connected in 60x-compatible mode without
losing functionality and performance. It also makes it easy to connect other 60x-compatible slaves on the
60x bus.
11.2.11 External Address Latch Enable Signal (ALE)
The memory controller provides control for an external address latch, needed on the 60x bus in 60x
compatible mode. ALE is asserted for one clock cycle on the first cycle of each memory-controller
transaction. In this section, whenever ALE is not on a timing diagram, assume that it is asserted on the first
cycle in which CS can be asserted.
NOTE
ALE is relevant only on the 60x bus and only in 60x-compatible mode.
11.2.12 ECC/Parity Byte Select (PBSE)
Systems that use ECC or read-modify-write parity, require an additional memory device that requires
byte-select like a normal data device. ANDing BS[0–7] through external logic to achieve the logical
function of this byte-select can affect the memory access timing because it adds a delay to the byte-select
path. The PowerQUICC II’s memory controller provides optional byte-select pins that are an internal
AND of the eight byte selects, allowing glueless, faster connection to ECC/RMW-parity devices.
This option is enabled by setting SIUMCR[PBSE], as described in Section 4.3.2.6, “SIU Module
Configuration Register (SIUMCR).”