Freescale Semiconductor MPC8260 - Manual (Page 796)

SCC Ethernet Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
25-12 Freescale Semiconductor
address, address recognition can be performed on multiple group addresses using the GADDRn hash table.
In promiscuous mode, the controller receives all incoming frames regardless of their address, unless
REJECT is asserted.
If an external CAM is used for address recognition, select promiscuous mode; the frame can be rejected
by asserting REJECT while the frame is being received. The on-chip address recognition functions can be
used in addition to the external CAM address recognition functions.
If the external CAM stores addresses that should be rejected rather than accepted, the use of REJECT by
the CAM should be logically inverted.
25.11 Hash Table Algorithm
Individual and group hash filtering operate using certain processes. The Ethernet controller maps any
48-bit address into one of 64 bins, each represented by a bit stored in GADDRx or IADDRx. When a
SET
GROUP ADDRESS command is executed, the Ethernet controller maps the selected 48-bit address into one
of the 64 bits by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting 6 bits
of the CRC-encoded result to generate a number between 1 and 64. Bits 31–30 of the CRC result select
one of the GADDRs or IADDRs; bits 29–26 of the CRC result indicate the bit in that register.
When the Ethernet controller receives a frame, the same process is used. If the CRC generator selects a bit
that is set in the group/individual hash table, the frame is accepted. Otherwise, it is rejected. So, if eight
group addresses are stored in the hash table and random group addresses are received, the hash table
prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. Frames that reach
memory must be further filtered by the processor to determine if they contain one of the eight preferred
addresses.
Better performance is achieved by using the group and individual hash tables simultaneously. For instance,
if eight group and eight physical addresses are stored in their respective hash tables, 87.5% of all frames
are prevented from reaching memory. The effectiveness of the hash table declines as the number of
addresses increases. For instance, with 128 addresses stored in a 64-bin hash table, the vast majority of the
hash table bits are set, thus preventing a small fraction of the frames from reaching memory.
Hash tables cannot be used to reject frames that match a set of entered addresses because unintended
addresses are mapped to the same bit in the hash table.
25.12 Interpacket Gap Time
The receiver receives back-to-back frames with a minimum interpacket spacing of 9.6 µs. In addition, after
the backoff algorithm, the transmitter waits for carrier sense to be negated before resending the frame.
Retransmission begins 9.6 µs after carrier sense is negated if it stays negated for at least 6.4 µs.
25.13 Handling Collisions
If a collision occurs as a frame is being sent, the Ethernet controller continues sending for at least 32 bit
times, thus sending a JAM pattern of 32 ones. If a collision occurs during the preamble sequence, the JAM
pattern is sent at the end of the sequence.