Freescale Semiconductor MPC8260 - Manual (Page 315)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-9
line, and disconnects after reading one cache line. If AD[1-0] is 0bx1 (a reserved encoding) and the
PCI_C/BE[3-0]
signals indicate a memory transaction, it executes a target disconnect after the first data
phase is completed. Note that AD[1-0] are included in parity calculations.
9.9.1.2.3 Byte Enable Signals
The byte enable signals (BE[3-0]) indicate which byte lanes carry valid data. The byte enable signals may
enable different bytes for each of the data phases. The byte enable signals are valid on the edge of the clock
that starts each data phase and remain valid for the entire data phase.
If the PCI bridge, as a target, sees no byte enable signals asserted, it completes the current data phase with
no permanent change. This implies that on a read transaction, the PCI bridge expects the data not to be
changed, and on a write transaction, the data is not stored.
9.9.1.2.4 Bus Driving and Turnaround
The turnaround-cycle is one clock cycle and is required to avoid contention. This cycle occurs at different
times for different signals. IRDY, TRDY, and DEVSEL use the address phase as their turnaround-cycle.
FRAME, PCI_C/BE[3-0], and AD[31-0] use the idle cycle between transactions as their turnaround-cycle.
(An idle cycle in PCI is when both FRAME and IRDY are negated.)
Byte lanes not involved in the current data transfer are driven to a stable condition even though the data is
not valid.
9.9.1.3 Bus Transactions
The timing diagrams in this section show the relationship of significant signals involved in bus
transactions.
Note the following conventions:
• When a signal is drawn as a solid line, it is actively being driven by the current initiator or target.
• When a signal is drawn as a dashed line, no agent is actively driving it.
• Three-stated signals with slashes between the two rails have indeterminate values.
• The terms ‘edge’ and ‘clock edge’ refer to the rising edge of the clock.
• The terms ‘asserted’ and ‘negated’ refer to the globally visible state of the signal on the clock edge,
and not to signal transitions.
• The symbol represents a turnaround-cycle.
9.9.1.3.1 Read and Write Transactions
Both read and write transactions begin with an address phase followed by a data phase. The address phase
occurs when FRAME is asserted for the first time, and the AD[31-0] signals contain a byte address and
the PCI_C/BE[3-0] signals contain a bus command. The data phase consists of the actual data transfer and
possible wait cycles; the byte enable signals remain actively driven from the first clock of the data phase
through the end of the transaction.